请知道的高手指点一下:latchup.guidance .3a:maximum spacefrom any point within source/drain region to the nearest pickup AA region inside the same well for I/O and internal circuits.
跑DRC提示上面的错误,说是latch问题,我改了几遍,都没有处理好,电路与版图如下,其中 nmos的DRC没问题,pmos的DRC不论怎么改,都说file:///C:\Users\王兆悦\Documents\Tencent Files\862805879\Image\C2C\6$9)}{PKZQKA3F~}746HFSQ.png以上这个问题,加粗漏端,在外面加两层guard ring 都没用。esd电路