Cadence 2016 校园招聘火热进行中

kengteng

Cadence 2016 校园招聘火热进行中


公司介绍

Cadence是一家电子设计自动化 (EDA)与半导体知识产权(IP)的领先供应商。我们的定制/模拟工具帮助工程师设计构成芯片级系统(SoCs)芯片的晶体管、标准单元和IP模块。我们的数字工具可对千兆级、千兆赫兹及最新半导体工艺节点的SoC进行自动化设计和验证。我们的IC封装和PCB工具可实现完整的电路板和子系统的设计。
Cadence还提供用于存储器、接口协议、模拟/混合信号组件和专业处理器设计IP和验证IP不断增长的产品。在系统层面，Cadence提供一个集成的硬件/软件套件协同开发平台。总之，Cadence的创新技术在创造改变生活的重大电子产品中起着至关重要的作用。


欲了解职位详情请查询“ 就业机会” of  www.cadence.com.cn或关注Cadence公众微信平台：Cadence微招聘



需求专业
微电子，电子信息工程，计算机，软件工程及相关专业的2016届毕业的硕士、博士生投递。

网申时间
9月1日-10月31日，欢迎通过http://www.dajie.com/corp/100372 ... /innerLink/26918501
进行网申。


空缺职位
若干软件研发工程师、产品验证工程师、产品工程师、前端设计工程师等职位空缺在上海和北京


上海

1.产品验证工程师 - 数字后端 (DSG)

职位描述：
(1)验证数字后端EDA工具Encounter/Innovus，确保产品在整个后端设计流程中可以正确工作，实现各个步骤的设计目标并满足性能要求,签字认可产品发布。

职位需求：
(1)熟练掌握微电子专业的基础知，深入理解时序功耗分析优化，超大规模集成电路制造工艺原理，先进制程设计规则者优先
(2)熟悉IC设计流程，有使用EDA工具（Cadence/Synopsys/Magma/Mentor）经验者优先
(3)熟悉Linux/Unix工作环境，熟悉perl/tcl/csh等，有脚本设计经验及自动化测试经验者优先
(4)具备良好的自学能力和团队协作精神。
(5)本科及以上学历，英文读写流利，听说熟练。

Senior Product Validation Engineer (DSG)

Position Description:
Validate the digital backend EDA tool Encounter/Innovus, sign off on the functional correctness of Encounter/Innovus throughout the backend design flow, sign off on the performance and QoR (Quality of Results) for each flow steps and engines, and sign off on product release to customer

Position Requirements:
(1)Solid academic background on Micro-Electronics. In-depth understanding into Timing/Power Analysis & Optimization, VLSI manufacture process theory, or advanced manufacture design rule is highly preferred
(2)Being familiar with IC design flow, experience with EDA tool usage (Cadence/Synopsys/Mentor/Magma) is highly preferred
(3)Being familiar with Linux/Unix platform and scripting languages (i.e. Perl/Tcl/Csh), experience with scripting design or automatic test/regression is highly preferred
(4)Good self-learner and team-player
(5)Bachelor degree or above, being fluent in both oral and literal English

2.产品工程师 - 数字后端 (DSG)

职位描述：
设计开发数字后端工具Encounter/Innovus，并对Cadence亚太及全球数字后端业务提供技术支持。

职位需求：
(1)熟练掌握微电子专业的基础知，深入理解时序功耗分析优化，超大规模集成电路制造工艺原理，先进制程设计规则者优先
(2)熟悉IC设计流程，有使用EDA工具（Cadence/Synopsys/Magma/Mentor）经验者优先
(3)熟悉Linux/Unix工作环境，熟悉perl/tcl/csh等，有脚本设计经验及自动化测试经验者优先
(4)具备良好的自学能力和团队协作精神。
(5)本科及以上学历，英文读写流利，听说熟练。

Senior Product Engineer (DSG)

Position Description：
Design and develop digital backend tool Encounter/Innovus. Provide technical support for Cadence AP and worldwide business.

Position Requirements:
(1)Solid academic background on Micro-Electronics. In-depth understanding into Timing/Power Analysis & Optimization, VLSI manufacture process theory, or advanced manufacture design rule is highly preferred
(2)Being familiar with IC design flow, experience with EDA tool usage (Cadence/Synopsys/Mentor/Magma) is highly preferred
(3)Being familiar with Linux/Unix platform and scripting languages (i.e. Perl/Tcl/Csh), experience with scripting design or automatic test/regression is highly preferred
(4)Good self-learner and team-player
(5)Bachelor degree or above, being fluent in both oral and literal English

3.前端工程师 (IPG)
职位描述：
(1)负责IP和SoC设计, 验证和实现.
(2)日常工作: 数字芯片设计微架构, RTL 编程, 逻辑综合, 功能验证, 测试, 和静态时序分析.
(3)硬件描述语言, 掌握verilog 或 vhdl.
(4)熟悉C/C++/perl/tcl/csh/python, UNIX, Linux.
(5)优秀的分析和解决问题的能力.对复杂的技术的问题有快速分析的能力，对新的知识有较强的学习能力.
(6)优秀的沟通能力和团对合作精神.
(7)积极主动, 有责任心.

职位需求：
(1)微电子,电子工程或计算机相关硕士以上学历
(2)既能独立工作也能团对合作
(3)较强的语言沟通能力,包含英语和中文.
(4)有以下经验者优先: asic 设计, FPGA 设计, 计算机体系架构, SOC 设计, DDR


Senior Design Engineer (IPG)
  
Position Description:
Deliver/implement IP and SoC chip. The engineer should be able to act as a good team member and contributor
Specific duties include:
-Proficiency in logic design, simulation, synthesis, STA and testing
-Proficiency in Verilog and its simulation environment
-Good knowledge of problem analysis/solving

Position Requirements:
(1)MS degree with 0~2 years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
(2)Essential that the individual demonstrates strong communication, verbal and written.
(3)Requires good communication skills in English.

4. 软件研发工程师 － 数字后端 (DSG)

职位描述:         
(1)负责开发和维护数字电路后端（物理）设计软件，包括数据库的维护、布局、布线及时序分析等。
(2)应用前沿的思想和算法改进当前软件，提高软件性能和质量。
(3)根据最新工艺发展，实现新功能，满足工艺发展需求。

职位需求:
(1)计算机,电子或者数学专业硕士及以上学历。
(2)精通Linux/Unix环境下的C/C++编程，具备扎实的数据算法功底，熟悉软件开发流程。
(3)有很好的团队合作精神，英文读写流利，听说熟练。
(4)工作积极热情，具有探索和创新精神。
(5)熟悉数字后端设计算法者优先。

Senior Software Engineer (DSG)

Position Descriptions:
(1)Maintain and develop backend EDA tools, including database, floor plan, place, route and optimization etc.
(2)Apply most advanced technologies and algorithms to improve the performance and quality of the tools.
(3)Add new features to fit quick developed manufactory needs.

Position Requirements:
(1)MS above in CS/EE or similar level of expertise with 3+ years of working experience.
(2)Excellent programming skills in C/C++ on Linux/Unix platform, script (csh, Tcl etc.) programming is a plus.
(3)Demonstrated problem-solving, architecture, algorithmic.
(4)Good team player with strong written and verbal communication skills.
(5)Strong desires to learn and explore new technologies.
(6)EDA software development experience or IC design knowledge is a plus.

5.软件研发工程师 — Palladium (SVG)

职位描述：
(1)参与 Palladium验证计算平台的调试工具开发。 Palladium是目前唯一一款基于处理器的全集成高性能验证计算平台，它在一个统一的验证环境中综合了模拟(Simulation)、加速(Acceleration)与仿真(Emulation)。
(2)负责Palladium调试工具的图形界面的开发及维护。
(3)参与开发下一代验证计算平台的核心模块。

职位需求：
(1)精通C/C++程序设计语言，精通数据结构和算法，熟悉Java, Tcl/Tk 和Shell脚本程序设计，熟悉Linux/Unix开发环境
(2)熟悉多线程程序设计，有RPC和Socket编程经验者优先
(3)了解硬件设计语言Verilog或VHDL,具有数字电路逻辑设计知识者优先
(4)本科及以上学历，专业：EE/CS/CE ，英文读写流利，听说熟练，有团队合作精神，能够适应和世界各地开发人员一起工作的环境
(5)具有EDA/CAD行业工作经历或逻辑设计验证经验者优先


Senior Software Engineer (SVG)

Position Description:       
(1)Software engineer working in a team oriented environment to develop and maintain advanced emulation and co-simulation runtime software tools.
(2)Responsibilities include working on support and development of co-simulation runtime software for next generation emulation systems.
                               
Position Requirements:       
(1)Bachelor/Master Degree in EE/CS/CE
(2)C/C++, Data structure and Algorithm, Tcl/Tk and Unix shell programming skills.
(3)Prefer with experience of using Verilog/VHDL simulator.
(4)Good communication skills (prefer English language proficiency), attention to details, and ability to work in multi-site/multi-person project.
(5)EDA/CAD tool development experience or logic design verification experience.


6. 软件研发工程师(DSG-SVG)

职位描述：
(1)作为软件工程师，负责Cadence Voltus芯片电源完整性分析软件开发和维护。

职位需求：
(1)熟练使用C或C++，熟悉Linux/Unix开发环境
(2)精通数据结构和算法，了解数值算法或多线程编程优先
(3)有半导体知识、EDA软件使用或开发经验者优先
(4)微电子及相关专业硕士及以上学历，英文读写流利，听说熟练

Senior Software Engineer (DSG-SVG)

Position Description:
(1)Responsible for designing, developing, troubleshooting and debugging power analysis software.
(2)Works on extremely complex problems where analysis of situations or data requires an evaluation of intangible variance factors.
(3)Exercises independent judgment in developing methods, techniques, and evaluation criterion for obtaining results.
(4)Work leadership may be provided by assigning work and resolving problems
  
Position Requirements:
(1)The candidate should have MS/PhD in EE/CS, strong programming skills in C++, and deep familiarity with object-oriented programming methods.
(2)Prior knowledge and experience with multi-threaded programming, numerical analysis techniques, and in-depth understanding of VLSI chip power analysis preferred.


北京

1.软件研发工程师(CPG)

职位描述：
开发和维护Cadence模拟电路仿真器/特征化参数提取工具/模拟电路设计集成环境

职位需求：
(1)精通C++编程，熟悉Linux/Unix开发环境
(2)熟悉模拟电路设计优先
(3)熟悉如下相关语言优先：Spice, Verilog, Verilog-A, Verilog-AMS, VHDL-AMS
(4)熟悉GUI开发，特别有QT toolkit使用经验优先
(5)熟悉逻辑综合或静态时序分析相关知识优先


Senior Software Engineer (CPG)

Position Description:
Develop, enhance and maintain Cadence spice circuit simulator/cell characterization tool/Analog design environment

Position Requirements:
(1)Skilled in C++ programming, familiar with development under Linux/Unix environment;
(2)Familiar with analog design is a plus;
(3)Familiar with Spice, Verilog, Verilog-A, Verilog-AMS, VHDL-AMS language is a plus;
(4)Familiar with GUI development, especially using the Qt toolkit is a plus;
(5)Familiar with logic synthesis algorithms or STA is a plus


2.产品工程师 (CPG)

职位描述：
对Cadence MMSIM/AMS仿真器(包括APS, XPS, XPS-MS and AMS)提供深度技术支持
作为研发部分的一员，参与新技术的开发、测试、调试和推广

职位要求：
(1)模拟电路芯片设计及其相关专业硕士或者以上学历
(2)模拟电路设计方面、仿真和验证方面深厚的技术背景
(3)实际的模拟或者混合信号电路的设计和流片经验，包括PLL, data converter, Flash, SRAM, DRAM, custom digital, power management
(4)熟悉SPICE和快速SPICE仿真器技术的优先
(5)良好的英文交流能力

Senior Product Engineer (CPG)

Position Description:
To provide in-depth technical support for Cadence MMSIM/AMS simulators including APS, XPS, XPS-MS and AMS;
To be part of R&D for new technology development by circuit debugging, testing and rollout.

Position Requirements:
(1) Education Requirement MS or above in analog IC design or related fields;
(2) Strong background in circuit design, simulation and verification;
(3) Hands-on experience in analog or mixed signal design, including PLL, data converter, Flash, SRAM, DRAM, custom digital, power management, etc, is a MUST;
(4) Familiar with SPICE and fast SPICE simulation technology is a big plus;
(5) Good communication in written and oral English required.

老阮

已投，什么时候会有消息啊

hymeng98

回复 2# 老阮

在大街网上看到，好像10月17号上海会有宣讲，笔试。感觉Cadence的HR很好，投过简历后，他们会打电话确认一下一些基本情况，这样好歹知道他们看到简历了。
这个不错，投了这么多家公司，就Cadence有这样的反馈，赞一个！！

qianyuji

回复 3# hymeng98


   你是什么时候接到的HR电话啊？之后还有消息吗？   我是上上周五接到的，然后就没有然后了。。不会被HR给刷了吧，囧

qianyuji

回复 2# 老阮


    咦，好巧，哈哈！

qianyuji

回复 3# hymeng98


   你接过HR的电话之后，还有后续通知吗？   我上上周五接到的，然后就没有然后了

hymeng98

回复 6# qianyuji

没消息了，应该还早吧，我觉得应该到十月中旬了。

riz.pde

no news, it should still early, and I think it should be up to mid-October.