请教一个DC的问题，DC做STA，某一或非门异常大，请各位大神分析一下

fruitwolf · 发表于 2015-8-25 16:09:36

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各位大神：    本人在使用DC综合一个自己写的电路时，出现了某一或非门延迟异常大，22ns的情况，请教一下各位大神，应该从哪些方面去考虑解决这个问题。
   时序路径如下：
  ****************************************
Report : timing
      -path full
      -delay max
      -max_paths 1
Design : openmips
Version: H-2013.03-SP1
Date : Tue Aug 25 16:01:28 2015
****************************************

# A fanout number of 1000 was used for high fanout net computations.

Operating Conditions: typical Library: smic18_tt
Wire Load Model Mode: segmented

  Startpoint: if_id0/id_inst_reg[29]
            (rising edge-triggered flip-flop clocked by clk)
  Endpoint: id_ex0/ex_aluop_reg[0]
         (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Des/Clust/Port    Wire Load Model    Library
  ------------------------------------------------
  CP0             reference_area_20000  smic18_tt
  LLbit             reference_area_20000  smic18_tt
  hilo_reg          reference_area_20000  smic18_tt
  mem_wb          reference_area_20000  smic18_tt
  ex_mem          reference_area_100000 smic18_tt
  div             reference_area_100000 smic18_tt
  id_ex             reference_area_20000  smic18_tt
  regfile          reference_area_1000000
                                       smic18_tt
  IF_ID             reference_area_20000  smic18_tt
  openmips          reference_area_1000000
                                       smic18_tt
  pc                reference_area_20000  smic18_tt
  ID                reference_area_100000 smic18_tt
  ctrl             reference_area_20000  smic18_tt

  Point                                  Incr    Path
  -----------------------------------------------------------
  clock clk (rise edge)                   0.00    0.00
  clock network delay (ideal)             0.00    0.00
  if_id0/id_inst_reg[29]/CK (FFDHD4X)    0.00 #    0.00 r
  if_id0/id_inst_reg[29]/QN (FFDHD4X)    0.15    0.15 f
  if_id0/U5/Z (INVHD8X)                   0.07    0.22 r
  if_id0/id_inst[29] (IF_ID)             0.00    0.22 r
  id0/inst_i[29] (ID)                   0.00    0.22 r
  id0/U36/Z (AND4HD2X)                   0.16    0.39 r
  id0/U58/Z (AND2HD4X)                   0.11    0.49 r
  id0/U718/Z (NAND4B1HD2X)                0.15    0.65 r
  id0/U170/Z (OAI21HD4X)                0.09    0.74 f
  id0/U490/Z (NOR2HD1X)                22.04    22.78 r
  id0/U489/Z (XNOR2HD1X)                7.29    30.06 f
  id0/U484/Z (AND4HD1X)                   0.38    30.44 f
  id0/U482/Z (NAND2HD1X)                0.16    30.60 r
  id0/U214/Z (NAND2HD1X)                0.11    30.71 f
  id0/stall (ID)                         0.00    30.71 f
  control/stallreq_from_id (ctrl)       0.00    30.71 f
  control/U4/Z (AOI21B2HD2X)             0.37    31.08 f
  control/stall[2] (ctrl)                0.00    31.08 f
  id_ex0/stall[2] (id_ex)                0.00    31.08 f
  id_ex0/U215/Z (NOR3HD4X)                2.92    34.00 r
  id_ex0/U214/Z (NOR4B1HD4X)             2.44    36.44 f
  id_ex0/U209/Z (AOI22HDLX)             0.76    37.20 r
  id_ex0/U208/Z (INVHDPX)                0.03    37.23 f
  id_ex0/ex_aluop_reg[0]/D (FFDQHD1X)    0.00    37.23 f
  data arrival time                               37.23

  clock clk (rise edge)                20.00    20.00
  clock network delay (ideal)             0.00    20.00
  clock uncertainty                      -1.00    19.00
  id_ex0/ex_aluop_reg[0]/CK (FFDQHD1X)    0.00    19.00 r
  library setup time                   -0.43    18.57
  data required time                               18.57
  -----------------------------------------------------------
  data required time                               18.57
  data arrival time                               -37.23
  -----------------------------------------------------------
  slack (VIOLATED)                               -18.66

1

请各位大神分析一下，这个问题怎么解决