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发表于 2015-7-27 14:38:35
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回复 3# 18345175021
Before clock tree synthesis, clock uncertainty is caused by clock jitter, which is the variation in the clock edge times of the source clock, as well as clock skew, which is the difference in clock arrival times resulting from different propagation delays from the chip’s clock pins to different sequential devices in the chip. After clock tree synthesis, with propagated latency, the tool separately accounts for uncertainty resulting from different propagation delays through the clock tree.
我的理解是,CTS之后,每条线路应该有不同的uncertainty,skew应该已经是确定值了,这时候的uncertainty应该主要是考虑单独每条线路上的延时不确定值,这个主要是受线路上buffer和combinational logic的latency不确定性影响,具体值是多少其实厂商会给,原理我们应该不用懂。 |
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