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发表于 2015-7-24 14:47:10
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MWNL-297
NAME
MWNL-297 (Error) Module '%s' is not defined.
DESCRIPTION
This error message occurs when the specified module is not defined either in the Verilog source file(s) or as a FRAM view in reference libraries.
WHAT NEXT
If you want the tool to continue with undefined module, you can specify option "-allow_undefined_module" or option "-dirty_netlist", then a CEL will be created for the undefined module and read_verilog will continue. However, if the missing module is not what you intended, check the Verilog source file(s) and make sure all modules are either defined or exist in the reference libraries. |
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