库里有clock gating cell，为什么在DC中使用时报错

jiazhang

厂商手册上提到库中有clock gate cell



可是当我设置：   *是cell name
set_clock_gating_style \
        -positive_edge_logic {integrated:********} \
        -control_point before \
        -max_fanout 32 \
        -no_sharing \
        -minimum_bitwidth 4 \
        -sequential_cell latch

工具提示 Error: The library cell **** specified for use as an integrated clock-gating cell does not have the clock_gating_integrated cell attribute.The value required for this attribute is latch_posedege_precontrol (PWR-193)

于是我手动设置此属性：

set_attribute [get_lib_cells */********] clock_gating_integrated_cell  latch_posedge_precontrol

但在综合时，报错：
Error: Could not find the EN pin with the correct attribute on the specified integrated clock-gating cell ****. (PWR-199)
Error: Could not find the exact pin matches with the integrated clock-gating cell *******. (PWR-197)
Warning: Combinational cell 'main_gate' (GTECH_AND2) cannot be translated exactly into '*****'. (TRANS-8)
  Processing 'SNPS_CLOCK_GATE_HIGH_mem8_0'
  Mapping integrated clock gating circuitry

andeliev

请问楼主，上面的问题后来怎么解决的？我也遇到类似问题。