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本帖最后由 stillwind1982 于 2015-7-7 12:27 编辑
用PT做STA时，set timing_remove_clock_reconvergence_pessimism true，
report_timing时发现“data require time”中的“clock reconvergence pessimism”一项数值过大，远超当前工艺下的典型值
进一步report_crpr，发现PT的clock reconvergence pessimism算错了，报告如下：
****************************************
Report : CRP Calculation
Design : xxxxx
Version: H-2013.06
Date : xxxxxx
****************************************
Startpoint: xxxxxxx
(rising edge-triggered flip-flop clocked by clk)
Endpoint: xxxxxxxx
(recovery check against rising-edge clock clk)
Common Point: cts_funcINV12CK_G5B1I1/O
Common Clock: clk
Launching edge at common point: FALLING
Capturing edge at common point: FALLING
CRPR threshold: 0.02
Arrival Times (Static) Early Late CRP
---------------------------------------------------------------
Rise 1.64 1.51 0.00
Fall 0.00 1.49 1.49
---------------------------------------------------------------
Arrival Times (Dynamic) Early Late CRP
---------------------------------------------------------------
Rise 1.64 1.51 0.00
Fall 0.00 1.50 1.50
---------------------------------------------------------------
Selection Details
---------------------------------------------------------------
Arrival Times: Using Static Arrivals
Edge Match: Match, using fall CRP
---------------------------------------------------------------
clock reconvergence pessimism 1.49
细看报告，不难发现：
1. 在这个clock tree的common point，时钟的下降沿对应寄存器时钟端的上升沿;
2. PT在计算clock reconvergence pessimism时完全算错了，具体表现为上升沿的early > late,下降沿的early=0.
根据这个报告的特点，猜测计算错误是因为common point的时钟沿与寄存器的时钟沿相反导致的。为了印证这个猜想，我们在网表中做了ECO，将clock tree共有路径上的inverter由奇数个改为偶数个，再report_crpr，结果如下：
****************************************
Report : CRP Calculation
Design : xxxxx
Version: H-2013.06
Date : xxxxxx
****************************************
Startpoint: xxxxxxx
(rising edge-triggered flip-flop clocked by clk)
Endpoint: xxxxxxxx
(recovery check against rising-edge clock clk)
Common Point: cts_funcINV3CK_G5B2I1/O
Common Clock: clk
Launching edge at common point: RISING
Capturing edge at common point: RISING
CRPR threshold: 0.02
Arrival Times (Static) Early Late CRP
---------------------------------------------------------------
Rise 1.46 1.56 0.10
Fall 1.58 1.58 0.00
---------------------------------------------------------------
Arrival Times (Dynamic) Early Late CRP
---------------------------------------------------------------
Rise 1.46 1.57 0.10
Fall 1.57 1.58 0.01
---------------------------------------------------------------
Selection Details
---------------------------------------------------------------
Arrival Times: Using Static Arrivals
Edge Match: Match, using rise CRP
---------------------------------------------------------------
clock reconvergence pessimism 0.10
报告果然恢复了正常。那么问题来了，在一个正常的IC项目中，clock tree的共有路径成千上万，我们不可能靠肉眼一一检查，更不可能通过类似上面的ECO的方式一一解决。
如何使PT在common point的时钟沿与寄存器的时钟沿相位相反的情况下也可以正确的计算clock reconvergence pessimism呢？
还请有相关经验的大神不吝赐教，万分感激！ |
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发表于 2015-7-7 09:47:48
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