saif_map -write_map ... (generate empty file)

shedo · 发表于 2015-7-5 21:48:12

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Hi all,
I'm trying to generate a "Name Mapping File" for primetime px, starting from a sldb description of "DW_ram_rw_s_dff.v". For normal design with verilog source I don't have any problems but if I use a sldb description (dw_foundation.sldb), design compiler generate an empty "Name Mapping File".
For the simulation I used the verilog code provided by synopsys.

This is my piece of code to generate the Name Mapping File:

saif_map -start
...
sh vcd2saif -input ../sim/rtlvcd.dump -output ./rtlvcd.saif
saif_map -review -create_map -source_instance test/u0 -input ./rtlvcd.saif
saif_map -report
saif_map -write_map ./aes_cipher_ptpxmap.tcl -type ptpx

复制代码

I attach my full script and the log.
syn.tcl.doc
tim_rtlvcd.tcl.doc
log_syn.doc

Do you have any idea how to solve the problem?
The presence of "Name Mapping File" affects a lot on the estimate of consumption?

Thanks for your help!

Heller_sun · 发表于 2015-11-24 09:15:07

楼主问题解决了吗，我也遇到同样问题，不知道如何解决

aureage · 发表于 2015-12-22 14:42:17

回复 1# shedo

Have u fixed this problem, sir ?
I have met the same fault

一力为侵 · 发表于 2015-12-22 14:46:02

同问～

juneshang · 发表于 2016-11-30 13:13:12

同问~~

段智2016 · 发表于 2018-3-15 21:12:30

很好,值得一看

段智2016 · 发表于 2018-3-15 21:13:40

不错的东西

[调查] saif_map -write_map ... (generate empty file)

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