saif_map -write_map ... (generate empty file)

shedo

Hi all,
I'm trying to generate a "Name Mapping File" for primetime px, starting from a sldb description of "DW_ram_rw_s_dff.v". For normal design with verilog source I don't have any problems but if I use a sldb description (dw_foundation.sldb), design compiler generate an empty "Name Mapping File".
For the simulation I used the verilog code provided by synopsys.

This is my piece of code to generate the Name Mapping File:

1. saif_map -start
   
2. ...
   
3. sh vcd2saif -input ../sim/rtlvcd.dump -output ./rtlvcd.saif
   
4. saif_map -review -create_map -source_instance test/u0 -input ./rtlvcd.saif
   
5. saif_map -report
   
6. saif_map -write_map ./aes_cipher_ptpxmap.tcl -type ptpx
   

复制代码

I attach my full script and the log.
syn.tcl.doc
tim_rtlvcd.tcl.doc
log_syn.doc

Do you have any idea how to solve the problem?
The presence of "Name Mapping File" affects a lot on the estimate of consumption?

Thanks for your help!

Heller_sun

楼主问题解决了吗，我也遇到同样问题，不知道如何解决

aureage

回复 1# shedo


Have u fixed this problem, sir ?
I have met the same fault

一力为侵

同问～

juneshang

同问~~

段智2016

很好,值得一看

段智2016

不错的东西