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按照协议写的，上板子一调24lc02不回ack,检查了下器件地址是对的，电压对应的时钟也是对的。哪位大侠帮忙看看代码。
`timescale 1ns/100ps
module IIC(
// inputs
clockCore,
resetCore,
sw1,
sw2,
// outputs
scl,
rdDataValid,
rdData,
// inout
sda
);
input clockCore;
input resetCore;
input sw1;
input sw2;
output scl;
output rdDataValid;
output [7:0] rdData;
reg rdDataValid;
reg [7:0] rdData;
inout sda;
parameter WRIDLE = 7'b0000001;
parameter WRSTART = 7'b0000010;
parameter WRCTRL = 7'b0000100;
parameter WRADDR = 7'b0001000;
parameter WRDATA = 7'b0010000;
parameter WRACK = 7'b0100000;
parameter WRSTOP = 7'b1000000;
parameter TESTDATA = 8'ha5; // TODO:change into data input
// write process
reg sw1F;
reg sw1F1;
reg wrEn;
reg [1:0] wrSlot;
reg sclWr;
reg sdaWr;
reg [6:0] wrState;
reg [6:0] nxtWrState;
reg [1:0] ackCnt;
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
sw1F <= 1'b1;
sw1F1 <= 1'b1;
end
else begin
sw1F <= sw1;
sw1F1 <= sw1F;
end
end
wire sw1Up = sw1F & ~sw1F1;
reg sw1UpF;// F1
reg sw1UpF2;
reg sw1UpF3;
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
sw1UpF <= 1'b0;
sw1UpF2 <= 1'b0;
sw1UpF3 <= 1'b0;
end
else begin
sw1UpF <= sw1Up;
sw1UpF2 <= sw1UpF;
sw1UpF3 <= sw1UpF2;
end
end
reg [3:0] wrStateCnt;
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
wrEn <= 1'b0;
end
else begin
if(wrState == WRSTOP && wrSlot == 2'd0)begin
wrEn <= 1'd0;
end
else if(sw1UpF2)begin
wrEn <= 1'b1;
end
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
wrSlot <= 2'b0;
end
else begin
if(wrState == WRSTOP && wrSlot == 2'd0)begin
wrSlot <= 2'd0;
end
else if(wrEn)begin
wrSlot <= wrSlot + 2'd1;;
end
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
wrStateCnt <= 4'd0;
end
else begin
if(wrStateCnt == 4'd8 && wrSlot == 2'd0)begin
wrStateCnt <= 4'd0;
end
else if(!wrEn)begin
wrStateCnt <= 4'd0;
end
else if(wrEn && wrSlot == 2'd0)begin
wrStateCnt <= wrStateCnt + 4'd1;
end
end
end
reg [7:0] address;
reg [7:0] addressLock;
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
address <= 8'd0;
addressLock <= 8'd0;
end
else begin
if(sw1Up) begin
addressLock <= address;
address <= address + 8'd1;
end
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
ackCnt <= 2'd0;
end
else begin
if(wrState == WRSTART)begin
ackCnt <= 2'd0;
end
else if(wrState == WRACK && wrSlot == 2'd0)
ackCnt <= ackCnt + 2'd1;
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
wrState <= WRIDLE;
end
else begin
wrState <= nxtWrState;
end
end
always @(*)begin
nxtWrState = wrState;
sclWr = 1'b1;
sdaWr = 1'b1;
case(wrState)
WRIDLE:begin
if(sw1Up) nxtWrState = WRSTART;
else nxtWrState = WRIDLE;
end
WRSTART:begin
if(sw1UpF) begin
nxtWrState = WRSTART;
sclWr = 1'b1;
sdaWr = 1'b0;
end
else if(sw1UpF2)begin
nxtWrState = WRSTART;
sclWr = 1'b1;
sdaWr = 1'b0;
end
else if(sw1UpF3)begin
nxtWrState = WRCTRL;
sclWr = 1'b0;
sdaWr = 1'b0;
end
end
WRCTRL:begin
if(wrStateCnt == 4'd8)begin // 1010001_0
case(wrSlot)
2'b00:begin
sclWr = 1'b0;
sdaWr = 1'b0;
nxtWrState = WRACK;
end
2'b01:begin
sclWr = 1'b0;
sdaWr = 1'b0;
nxtWrState = WRCTRL;
end
2'b10:begin
sclWr = 1'b1;
sdaWr = 1'b0;
nxtWrState = WRCTRL;
end
2'b11:begin
sclWr = 1'b1;
sdaWr = 1'b0;
nxtWrState = WRCTRL;
end
endcase
end
else if(wrStateCnt == 4'd1) begin // 1_0100010
nxtWrState = WRCTRL;
case(wrSlot)
2'b00:begin
sclWr = 1'b0;
sdaWr = 1'b1;
end
2'b01:begin
sclWr = 1'b0;
sdaWr = 1'b1;
end
2'b10:begin
sclWr = 1'b1;
sdaWr = 1'b1;
end
2'b11:begin
sclWr = 1'b1;
sdaWr = 1'b1;
end
endcase
end
else if(wrStateCnt == 4'd2)begin
nxtWrState = WRCTRL;
case(wrSlot)
2'b00:begin
sclWr = 1'b0;
sdaWr = 1'b0;
end
2'b01:begin
sclWr = 1'b0;
sdaWr = 1'b0;
end
2'b10:begin
sclWr = 1'b1;
sdaWr = 1'b0;
end
2'b11:begin
sclWr = 1'b1;
sdaWr = 1'b0;
end
endcase
end
else if(wrStateCnt == 4'd3)begin
nxtWrState = WRCTRL;
case(wrSlot)
2'b00:begin
sclWr = 1'b0;
sdaWr = 1'b1;
end
2'b01:begin
sclWr = 1'b0;
sdaWr = 1'b1;
end
2'b10:begin
sclWr = 1'b1;
sdaWr = 1'b1;
end
2'b11:begin
sclWr = 1'b1;
sdaWr = 1'b1;
end
endcase
end
else if(wrStateCnt == 4'd4)begin
nxtWrState = WRCTRL;
case(wrSlot)
2'b00:begin
sclWr = 1'b0;
sdaWr = 1'b0;
end
2'b01:begin
sclWr = 1'b0;
sdaWr = 1'b0;
end
2'b10:begin
sclWr = 1'b1;
sdaWr = 1'b0;
end
2'b11:begin
sclWr = 1'b1;
sdaWr = 1'b0;
end
endcase
end
else if(wrStateCnt == 4'd5)begin
nxtWrState = WRCTRL;
case(wrSlot)
2'b00:begin
sclWr = 1'b0;
sdaWr = 1'b0;
end
2'b01:begin
sclWr = 1'b0;
sdaWr = 1'b0;
end
2'b10:begin
sclWr = 1'b1;
sdaWr = 1'b0;
end
2'b11:begin
sclWr = 1'b1;
sdaWr = 1'b0;
end
endcase
end
else if(wrStateCnt == 4'd6)begin
nxtWrState = WRCTRL;
case(wrSlot)
2'b00:begin
sclWr = 1'b0;
sdaWr = 1'b0;
end
2'b01:begin
sclWr = 1'b0;
sdaWr = 1'b0;
end
2'b10:begin
sclWr = 1'b1;
sdaWr = 1'b0;
end
2'b11:begin
sclWr = 1'b1;
sdaWr = 1'b0;
end
endcase
end
else if(wrStateCnt == 4'd7)begin
nxtWrState = WRCTRL;
case(wrSlot)
2'b00:begin
sclWr = 1'b0;
sdaWr = 1'b1;
end
2'b01:begin
sclWr = 1'b0;
sdaWr = 1'b1;
end
2'b10:begin
sclWr = 1'b1;
sdaWr = 1'b1;
end
2'b11:begin
sclWr = 1'b1;
sdaWr = 1'b1;
end
endcase
end
end
WRADDR:begin
if(wrStateCnt == 4'd8)begin
case(wrSlot)
2'b00:begin
sclWr = 1'b0;
nxtWrState = WRACK;
sdaWr = addressLock[0];
end
2'b01:begin
sclWr = 1'b0;
nxtWrState = WRADDR;
sdaWr = addressLock[0];
end
2'b10:begin
sclWr = 1'b1;
nxtWrState = WRADDR;
sdaWr = addressLock[0];
end
2'b11:begin
sclWr = 1'b1;
nxtWrState = WRADDR;
sdaWr = addressLock[0];
end
endcase
end
else if(wrStateCnt == 4'd1)begin
sdaWr = addressLock[7];
nxtWrState = WRADDR;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt == 4'd2)begin
sdaWr = addressLock[6];
nxtWrState = WRADDR;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt == 4'd3)begin
sdaWr = addressLock[5];
nxtWrState = WRADDR;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt == 4'd4)begin
sdaWr = addressLock[4];
nxtWrState = WRADDR;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt == 4'd5)begin
sdaWr = addressLock[3];
nxtWrState = WRADDR;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt == 4'd6)begin
sdaWr = addressLock[2];
nxtWrState = WRADDR;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt == 4'd7)begin
sdaWr = addressLock[1];
nxtWrState = WRADDR;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
end
WRDATA:begin
if(wrStateCnt == 4'd8)begin
case(wrSlot)
2'b00:begin
sclWr = 1'b0;
nxtWrState = WRACK;
sdaWr = TESTDATA[0];
end
2'b01:begin
sclWr = 1'b0;
nxtWrState = WRDATA;
sdaWr = TESTDATA[0];
end
2'b10:begin
sclWr = 1'b1;
nxtWrState = WRDATA;
sdaWr = TESTDATA[0];
end
2'b11:begin
sclWr = 1'b1;
nxtWrState = WRDATA;
sdaWr = TESTDATA[0];
end
endcase
end
else if(wrStateCnt == 4'd1)begin
sdaWr = TESTDATA[7];
nxtWrState = WRDATA;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt == 4'd2)begin
sdaWr = TESTDATA[6];
nxtWrState = WRDATA;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt == 4'd3)begin
sdaWr = TESTDATA[5];
nxtWrState = WRDATA;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt ==4'd4)begin
sdaWr = TESTDATA[4];
nxtWrState = WRDATA;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt == 4'd5)begin
sdaWr = TESTDATA[3];
nxtWrState = WRDATA;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt == 4'd6)begin
sdaWr = TESTDATA[2];
nxtWrState = WRDATA;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
else if(wrStateCnt == 4'd7)begin
sdaWr = TESTDATA[1];
nxtWrState = WRDATA;
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
end
WRACK: begin
sdaWr = 1'bz;
if(wrSlot == 2'd0)begin
if(ackCnt == 2'd0)begin
nxtWrState = WRADDR;
end
else if(ackCnt == 2'd1)begin
nxtWrState = WRDATA;
end
else if(ackCnt == 2'd2)begin
nxtWrState = WRSTOP;
end
end
else begin
nxtWrState = WRACK;
end
case(wrSlot)
2'b00:sclWr = 1'b0;
2'b01:sclWr = 1'b0;
2'b10:sclWr = 1'b1;
2'b11:sclWr = 1'b1;
endcase
end
WRSTOP:begin
case(wrSlot )
2'b00: begin
nxtWrState = WRIDLE;
sclWr = 1'b1;
sdaWr = 1'b1;
end
2'b01: begin
nxtWrState = WRSTOP;
sclWr = 1'b0;
sdaWr = 1'b0;
end
2'b10: begin
nxtWrState = WRSTOP;
sclWr = 1'b1;
sdaWr = 1'b0;
end
2'b11: begin
nxtWrState = WRSTOP;
sclWr = 1'b1;
sdaWr = 1'b1;
end
endcase
end
endcase
end
///////////////Random Read//////////////
parameter RDIDLE = 9'b000000001,
RDSTART = 9'b000000010,
RDCTRL = 9'b000000100,
RDADDR = 9'b000001000,
RDRESTART = 9'b000010000,
RDRECTRL = 9'b000100000,
RDACK = 9'b001000000,
RDREAD = 9'b010000000,
RDSTOP = 9'b100000000;
reg [1:0] rdSlot;
reg rdEn;
reg sw2F;
reg sw2F1;
reg sclRd;
reg sdaRd;
reg [8:0] rdState;
reg [8:0] nxtRdState;
reg [1:0] rdAckCnt;
reg [3:0] rdStateCnt;
reg [7:0] rdDataTmp;
reg rdDataValidTmp;
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
rdDataTmp <= 8'd0;
end
else begin
if(rdState == RDREAD && rdSlot == 2'd3)begin
case(rdStateCnt)
4'd1: rdDataTmp <= {rdDataTmp[7:1],sdaRd};
4'd2: rdDataTmp <= {rdDataTmp[7:2],sdaRd,rdDataTmp[0]};
4'd3: rdDataTmp <= {rdDataTmp[7:3],sdaRd,rdDataTmp[1:0]};
4'd4: rdDataTmp <= {rdDataTmp[7:4],sdaRd,rdDataTmp[2:0]};
4'd5: rdDataTmp <= {rdDataTmp[7:5],sdaRd,rdDataTmp[3:0]};
4'd6: rdDataTmp <= {rdDataTmp[7:6],sdaRd,rdDataTmp[4:0]};
4'd7: rdDataTmp <= {rdDataTmp[7],sdaRd,rdDataTmp[5:0]};
4'd8: rdDataTmp <= {sdaRd,rdDataTmp[6:0]};
endcase
end
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
rdDataValidTmp <= 1'd0;
end
else begin
if(rdState == RDREAD && rdSlot == 2'd3 && rdStateCnt == 4'd8)
rdDataValidTmp <= 1'd1;
else
rdDataValidTmp <= 1'd0;
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
sw2F <= 1'b1;
sw2F1 <= 1'b1;
end
else begin
sw2F <= sw2;
sw2F1 <= sw2F;
end
end
wire sw2Up = sw2F & ~sw2F1;
reg sw2UpF; // F1
reg sw2UpF2;
reg sw2UpF3;
reg [7:0] rdAddr;
reg [7:0] rdAddrLock;
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
rdAddr <= 8'd0;
rdAddrLock <= 8'd0;
end
else begin
if(sw2Up) begin
rdAddr <= rdAddr + 8'd1;
rdAddrLock <= rdAddr;
end
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
sw2UpF <= 1'b0;
sw2UpF2 <= 1'b0;
sw2UpF3 <= 1'b0;
end
else begin
sw2UpF <= sw2Up;
sw2UpF2 <= sw2UpF;
sw2UpF3 <= sw2UpF2;
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
rdEn <= 1'b0;
end
else begin
if(rdState == RDSTOP && rdSlot == 2'd0)begin
rdEn <= 1'd0;
end
else if(sw2UpF2)begin
rdEn <= 1'b1;
end
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
rdSlot <= 2'd0;
end
else begin
if(rdState == RDSTOP && rdSlot == 2'd0)begin
rdSlot <= 2'd0;
end
else if(rdEn)begin
rdSlot <= rdSlot + 2'd1;
end
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
rdStateCnt <= 4'd0;
end
else begin
if(rdStateCnt == 4'd8 && rdSlot == 2'd0)begin
rdStateCnt <= 4'd0;
end
else if(rdState == RDRESTART && rdSlot == 2'd0)begin
rdStateCnt <= 4'd1;
end
else if(rdEn && rdSlot == 2'd0)begin
rdStateCnt <= rdStateCnt + 4'd1;
end
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
rdAckCnt <= 2'd0;
end
else begin
if(rdState == RDSTART)begin
rdAckCnt <= 2'd0;
end
else if(rdState == RDACK && rdSlot == 2'd0)begin
rdAckCnt <= rdAckCnt + 2'd1;
end
end
end
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
rdState <= RDIDLE;
end
else begin
rdState <= nxtRdState;
end
end
always @(*) begin
nxtRdState = rdState;
sclRd = 1'b1;
sdaRd = 1'b1;
case(rdState)
RDIDLE :begin
if(sw2Up) nxtRdState = RDSTART;
else nxtRdState = RDIDLE;
end
RDSTART :begin
if(sw2UpF)begin
nxtRdState = RDSTART;
sclRd = 1'b1;
sdaRd = 1'b1;
end
else if(sw2UpF2)begin
nxtRdState = RDSTART;
sclRd = 1'b1;
sdaRd = 1'b0;
end
else if(sw2UpF3)begin
nxtRdState = RDCTRL;
sclRd = 1'b0;
sdaRd = 1'b0;
end
end
RDCTRL :begin
if(rdStateCnt == 4'd8)begin
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b0;
nxtRdState = RDACK;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b0;
nxtRdState = RDCTRL;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b0;
nxtRdState = RDCTRL;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b0;
nxtRdState = RDCTRL;
end
endcase
end
else if(rdStateCnt == 4'd1)begin
nxtRdState = RDCTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
endcase
end
else if(rdStateCnt == 4'd2)begin
nxtRdState = RDCTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
endcase
end
else if(rdStateCnt == 4'd3)begin
nxtRdState = RDCTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
endcase
end
else if(rdStateCnt == 4'd4)begin
nxtRdState = RDCTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
endcase
end
else if(rdStateCnt == 4'd5)begin
nxtRdState = RDCTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
endcase
end
else if(rdStateCnt == 4'd6)begin
nxtRdState = RDCTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
endcase
end
else if(rdStateCnt == 4'd7)begin
nxtRdState = RDCTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
endcase
end
end
RDADDR :begin
if(rdStateCnt == 4'd8)begin
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
nxtRdState = RDACK;
sdaRd = rdAddrLock[0];
end
2'b01:begin
sclRd = 1'b0;
nxtRdState = RDADDR;
sdaRd = rdAddrLock[0];
end
2'b10:begin
sclRd = 1'b1;
nxtRdState = RDADDR;
sdaRd = rdAddrLock[0];
end
2'b11:begin
sclRd = 1'b1;
nxtRdState = RDADDR;
sdaRd = rdAddrLock[0];
end
endcase
end
else if(rdStateCnt == 4'd1)begin
sdaRd = rdAddrLock[7];
nxtRdState = RDADDR;
case(rdSlot)
2'b00:sclRd = 1'b0;
2'b01:sclRd = 1'b0;
2'b10:sclRd = 1'b1;
2'b11:sclRd = 1'b1;
endcase
end
else if(rdStateCnt == 4'd2)begin
sdaRd = rdAddrLock[6];
nxtRdState = RDADDR;
case(rdSlot)
2'b00:sclRd = 1'b0;
2'b01:sclRd = 1'b0;
2'b10:sclRd = 1'b1;
2'b11:sclRd = 1'b1;
endcase
end
else if(rdStateCnt == 4'd3)begin
sdaRd = rdAddrLock[5];
nxtRdState = RDADDR;
case(rdSlot)
2'b00:sclRd = 1'b0;
2'b01:sclRd = 1'b0;
2'b10:sclRd = 1'b1;
2'b11:sclRd = 1'b1;
endcase
end
else if(rdStateCnt == 4'd4)begin
sdaRd = rdAddrLock[4];
nxtRdState = RDADDR;
case(rdSlot)
2'b00:sclRd = 1'b0;
2'b01:sclRd = 1'b0;
2'b10:sclRd = 1'b1;
2'b11:sclRd = 1'b1;
endcase
end
else if(rdStateCnt == 4'd5)begin
sdaRd = rdAddrLock[3];
nxtRdState = RDADDR;
case(rdSlot)
2'b00:sclRd = 1'b0;
2'b01:sclRd = 1'b0;
2'b10:sclRd = 1'b1;
2'b11:sclRd = 1'b1;
endcase
end
else if(rdStateCnt == 4'd6)begin
sdaRd = rdAddrLock[2];
nxtRdState = RDADDR;
case(rdSlot)
2'b00:sclRd = 1'b0;
2'b01:sclRd = 1'b0;
2'b10:sclRd = 1'b1;
2'b11:sclRd = 1'b1;
endcase
end
else if(rdStateCnt == 4'd7)begin
sdaRd = rdAddrLock[1];
nxtRdState = RDADDR;
case(rdSlot)
2'b00:sclRd = 1'b0;
2'b01:sclRd = 1'b0;
2'b10:sclRd = 1'b1;
2'b11:sclRd = 1'b1;
endcase
end
end
RDRESTART:begin
if(rdSlot == 2'd0)begin
nxtRdState = RDRECTRL;
sclRd = 1'b0;
sdaRd = 1'b0;
end
else if(rdSlot == 2'd1) begin
nxtRdState = RDRESTART;
sclRd = 1'b0;
sdaRd = 1'b1;
end
else if(rdSlot == 2'd2) begin
nxtRdState = RDRESTART;
sclRd = 1'b1;
sdaRd = 1'b1;
end
else if(rdSlot == 2'd3) begin
nxtRdState = RDRESTART;
sclRd = 1'b1;
sdaRd = 1'b0;
end
end
RDRECTRL :begin
if(rdStateCnt == 4'd8)begin
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b1;
nxtRdState = RDACK;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b1;
nxtRdState = RDRECTRL;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b1;
nxtRdState = RDRECTRL;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b1;
nxtRdState = RDRECTRL;
end
endcase
end
else if(rdStateCnt == 4'd1)begin
nxtRdState = RDRECTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
endcase
end
else if(rdStateCnt == 4'd2)begin
nxtRdState = RDRECTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
endcase
end
else if(rdStateCnt == 4'd3)begin
nxtRdState = RDRECTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
endcase
end
else if(rdStateCnt == 4'd4)begin
nxtRdState = RDRECTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
endcase
end
else if(rdStateCnt == 4'd5)begin
nxtRdState = RDRECTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
endcase
end
else if(rdStateCnt == 4'd6)begin
nxtRdState = RDRECTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b0;
end
endcase
end
else if(rdStateCnt == 4'd7)begin
nxtRdState = RDRECTRL;
case(rdSlot)
2'b00:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b01:begin
sclRd = 1'b0;
sdaRd = 1'b1;
end
2'b10:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
2'b11:begin
sclRd = 1'b1;
sdaRd = 1'b1;
end
endcase
end
end
RDACK :begin
if(rdSlot == 2'd0)begin
if(rdAckCnt == 2'd0)begin
nxtRdState = RDADDR;
end
else if(rdAckCnt == 2'd1)begin
nxtRdState = RDRESTART;
end
else if(rdAckCnt == 2'd2)begin
nxtRdState = RDREAD;
end
end
else begin
nxtRdState = RDACK;
end
sdaRd = 1'bz;
case(rdSlot)
2'b00:sclRd = 1'b0;
2'b01:sclRd = 1'b0;
2'b10:sclRd = 1'b1;
2'b11:sclRd = 1'b1;
endcase
end
RDREAD :begin
sdaRd = 1'dz;
if(rdStateCnt == 4'd8 && rdSlot == 2'd0)begin
nxtRdState = RDSTOP;
end
else if(rdStateCnt == 4'd1)begin
nxtRdState = RDREAD;
end
else if(rdStateCnt == 4'd2)begin
nxtRdState = RDREAD;
end
else if(rdStateCnt == 4'd3)begin
nxtRdState = RDREAD;
end
else if(rdStateCnt == 4'd4)begin
nxtRdState = RDREAD;
end
else if(rdStateCnt == 4'd5)begin
nxtRdState = RDREAD;
end
else if(rdStateCnt == 4'd6)begin
nxtRdState = RDREAD;
end
else if(rdStateCnt == 4'd7)begin
nxtRdState = RDREAD;
end
case(rdSlot)
2'b00:sclRd = 1'b0;
2'b01:sclRd = 1'b0;
2'b10:sclRd = 1'b1;
2'b11:sclRd = 1'b1;
endcase
end
RDSTOP :begin
case(rdSlot )
2'b00: begin
nxtRdState = RDIDLE;
sclRd = 1'b1;
sdaRd = 1'b1;
end
2'b01: begin
nxtRdState = RDSTOP;
sclRd = 1'b0;
sdaRd = 1'b0;
end
2'b10: begin
nxtRdState = RDSTOP;
sclRd = 1'b1;
sdaRd = 1'b0;
end
2'b11: begin
nxtRdState = RDSTOP;
sclRd = 1'b1;
sdaRd = 1'b1;
end
endcase
end
endcase
end
assign scl = (wrEn|sw1UpF|sw1UpF2) ? sclWr : ((rdEn|sw2UpF2) ? sclRd : 1'b1);
assign sda = (wrEn|sw1UpF|sw1UpF2) ? sdaWr : ((rdEn|sw2UpF2) ? sdaRd : 1'b1);
always @(posedge clockCore or negedge resetCore)begin
if(!resetCore)begin
rdDataValid <= 1'd0;
rdData <= 8'd0;
end
else begin
rdDataValid <= rdDataValidTmp;
rdData <= rdDataTmp;
end
end
endmodule
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发表于 2015-6-26 15:16:52
