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发表于 2015-6-24 15:40:56
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本帖最后由 dzplay 于 2015-6-24 16:04 编辑
这个和处理器的ddr控制器相关吧,不知道楼主用的哪款处理器?——【补充】如果楼主读写前没有初始化ddr,但处理器的ECC_EN功能配置为有效;必然会出现ECC中断。
以下摘自freescale P3041的Design Consideration
ECC_EN ECC enable
Note that when HID1[RFXE] = 1, uncorrectable read errors (that is, multi-bit errors) cause the
assertion of core_fault_in, which causes the core to generate a machine check interrupt unless
HID1[RFXE] is disabled (by clearing HID1[RFXE] = 0). If RFXE is zero and an uncorrectable read
error occurs, ERR_DISABLE[MBED] must be cleared and ERR_INT_EN[MBEE] and ECC_EN
must be set to ensure an interrupt is generated.
0 No ECC errors are reported. No ECC interrupts are generated. (ECC is disabled).
1 ECC is enabled. |
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