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line_buffer编译正确,但运行仿真提示"altshift_taps_component : altshift_taps" is not bound.是为什么?求大神指点
- LIBRARY altera_mf;
- USE altera_mf.all;
- ENTITY line_buffer IS
- PORT
- (
- clock : IN STD_LOGIC ;
- shiftin : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- shiftout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- taps : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
- );
- END line_buffer;
- ARCHITECTURE SYN OF line_buffer IS
- SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
- SIGNAL sub_wire1 : STD_LOGIC_VECTOR (23 DOWNTO 0);
- COMPONENT altshift_taps
- GENERIC (
- lpm_hint : STRING;
- lpm_type : STRING;
- intended_device_family : STRING;
- number_of_taps : NATURAL;
- power_up_state : STRING;
- tap_distance : NATURAL;
- width : NATURAL
- );
- PORT (
- clock : IN STD_LOGIC ;
- shiftin : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
- shiftout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
- taps : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
- );
- END COMPONENT;
- BEGIN
- shiftout <= sub_wire0(7 DOWNTO 0);
- taps <= sub_wire1(23 DOWNTO 0);
- ALTSHIFT_TAPS_component : ALTSHIFT_TAPS
- GENERIC MAP (
- -- intended_device_family => "Cylone II",
- lpm_hint => "RAM_BLOCK_TYPE=M4K",
- lpm_type => "altshift_taps",
- intended_device_family => "Cylone II",
- number_of_taps => 3,
- power_up_state => "CLEARED",
- tap_distance => 640,
- width => 8
- )
- PORT MAP (
- clock => clock,
- shiftin => shiftin,
- shiftout => sub_wire0,
- taps => sub_wire1
- );
- END SYN;
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