Verilog实现上升沿开始计数，下个上升沿停止计数

Myra1993

如题，用来测量脉冲信号周期，编译后错误是
Error (10133): Verilog HDL Expression error at Period.v(26): illegal part select of unpacked array "cnt"
程序如下：
module Period(
    clk,
    rst_n,
    signal,
    percounter
    );
input clk, rst_n, signal;
output signed [9:0] percounter;
reg  [9:0] percounter;
reg  signal_reg;
reg  cnt[9:0];
wire signal_pos;
always @ ( posedge clk or negedge rst_n ) begin
     if ( !rst_n )  begin
         signal_reg <= 1'b0;
     end
     else begin
         signal_reg <= signal;
     end
end

assign signal_pos = signal & (~signal_reg);

always @ ( posedge clk or negedge rst_n ) begin
     if ( !rst_n ) begin
         cnt[9:0] <= 10'd0;
     end
     else if ( signal_pos == 1'b1 ) begin
         cnt[9:0] <= 10'd0;
     end
     else begin
         cnt[9:0] <= cnt[9:0] + 10'd1;
     end
end

always @ ( posedge clk or negedge rst_n ) begin
     if ( !rst_n ) begin
         percounter[9:0] <= 10'd0;
     end
     else if ( signal_pos == 1'b1 ) begin
         percounter[9:0] <= cnt[9:0];
     end
     else begin
  
     end
end

endmodule

求大神帮忙看看怎么改，不胜感谢~~

白色de小牙刷

reg  cnt[9:0]
reg [9:0] cnt

h646598660

module Period(
    clk,
    rst_n,
    signal,
    percounter
    );
input clk, rst_n, signal;
output [9:0] percounter;
reg  [9:0] percounter;
reg  signal_reg;
reg  start;  //0 stop,1 start
wire signal_pos;
always @ ( posedge clk or negedge rst_n ) begin
     if ( !rst_n )  begin
         signal_reg <= 1'b0;
     end
     else begin
         signal_reg <= signal;
     end
end

assign signal_pos = signal & (~signal_reg);

always @ ( posedge clk or negedge rst_n ) begin
     if ( !rst_n ) begin
         start <= 1'b0;
     end
     else if ( signal_pos == 1'b1 ) begin
         start <= ~start;
     end
end

always @ ( posedge clk or negedge rst_n ) begin
     if ( !rst_n ) begin
         percounter[9:0] <= 10'd0;
     end
     else if ( start == 1'b1 ) begin
          percounter <= percounter + 10'b1;
     end
     else begin
          percounter <= percounter ;
          //precounter <= 10'b0      ; //clr or keep
     end
end

endmodule