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发表于 2015-4-27 20:19:42
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本帖最后由 redleaf1988 于 2015-4-27 20:22 编辑
回复 9# huangxjmail
我花了一下午时间,把master中的状态机,整合一遍,自己想了一些在组合逻辑中,减少延时的方法,把组合逻辑切断,通过用寄存器。具体考虑到我master中的设计,组合逻辑,我在if else 语句的条件中,用的很多,我定义了许多寄存器,但还是组合逻辑,没有打拍子,如果打上拍子,用时序逻辑做,逻辑上的时序就出问题,出不来要的时序。
我是这么做的 ,例如:
reg nseq_seq_last; always @( state or nseq_seq)
if( state== LAST | nseq_seq )
nseq_seq_last = 1'b1;
else
nseq_seq_last = 1'b0;
reg breq_nseq_seq_last;
always @( state or nseq_seq_last)
if( state== BREQ | nseq_seq_last )
breq_nseq_seq_last = 1'b1;
else
breq_nseq_seq_last = 1'b0;
我定义了很多这样的寄存器,目的把多个组合逻辑分开算,思想是这样的 ,因为组合逻辑主要在if else条件语句中,如:if(a+b+c)
通过定义: reg a1; 再定义a2: 让a1=a+b; 再算 a1+a2; 一直这么做,将代码中 所有if else 条件判断语句,都这么替换啦,最后后仿真,modelsim
出现
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:138710 ps, posedge I &&& (in_clk_enable1 != 0):138801 ps, 129 ps );
# Time: 138801 ps Iteration: 0 Instance: /tb_top/Top/\m1/write1_reg
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:208795 ps, posedge I &&& (in_clk_enable1 != 0):208846 ps, 129 ps );
# Time: 208846 ps Iteration: 0 Instance: /tb_top/Top/\m1/data_4
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:228710 ps, negedge I &&& (in_clk_enable1 != 0):228801 ps, 129 ps );
# Time: 228801 ps Iteration: 0 Instance: /tb_top/Top/\m1/write1_reg
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:368710 ps, posedge I &&& (in_clk_enable1 != 0):368801 ps, 129 ps );
# Time: 368801 ps Iteration: 0 Instance: /tb_top/Top/\m1/write1_reg
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:368795 ps, negedge I &&& (in_clk_enable1 != 0):368846 ps, 129 ps );
# Time: 368846 ps Iteration: 0 Instance: /tb_top/Top/\m1/data_4
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:528795 ps, posedge I &&& (in_clk_enable1 != 0):528846 ps, 129 ps );
# Time: 528846 ps Iteration: 0 Instance: /tb_top/Top/\m1/data_4
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:588710 ps, negedge I &&& (in_clk_enable1 != 0):588801 ps, 129 ps );
# Time: 588801 ps Iteration: 0 Instance: /tb_top/Top/\m1/write1_reg
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:688795 ps, negedge I &&& (in_clk_enable1 != 0):688846 ps, 129 ps );
# Time: 688846 ps Iteration: 0 Instance: /tb_top/Top/\m1/data_4
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:758710 ps, posedge I &&& (in_clk_enable1 != 0):758801 ps, 129 ps );
# Time: 758801 ps Iteration: 0 Instance: /tb_top/Top/\m1/write1_reg
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:808710 ps, negedge I &&& (in_clk_enable1 != 0):808801 ps, 129 ps );
# Time: 808801 ps Iteration: 0 Instance: /tb_top/Top/\m1/write1_reg
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:848795 ps, posedge I &&& (in_clk_enable1 != 0):848846 ps, 129 ps );
# Time: 848846 ps Iteration: 0 Instance: /tb_top/Top/\m1/data_4
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(103): $hold( posedge CLK:858710 ps, posedge I &&& (in_clk_enable1 != 0):858801 ps, 129 ps );
# Time: 858801 ps Iteration: 0 Instance: /tb_top/Top/\m1/write1_reg
# ** Error: D:/Xilinx/14.6/ISE_DS/ISE/verilog/src/simprims/X_FF.v(104): $hold( posedge CLK:948795 ps, negedge I &&& (in_clk_enable1 != 0):948846 ps, 129 ps );
# Time: 948846 ps Iteration: 0 Instance: /tb_top/Top/\m1/data_4
结合,仿真出的信息,我应该怎么做、?
大神,结合实际信息,下一步 我应该怎么做?
后仿真,以前没做过,进行fpga板级验证之前,后仿真得先过的,不知道咋做了 |
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