招聘后端工程师

Cissy_pq

后端经理JD：

公司因为高速发展，需要招聘后端设计经理/工程师一名。资历优秀的可以考虑高级经理。

- Perform physical design implementation,including floor planning, power grid design, place and route, clock treesynthesis, timing closure, power/signal integrity signoff, physicalverification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure and able to createthe GDSII for tape out - The candidate will have the opportunity to work onmany varieties of challenging design projects.

- Ability to handle large sized designimplementation tasks alone

Requirements:

-Must have hands on physical design and verification experience in the past twoyears in large scale ASIC chip physical design, 28 nm experience is preferred

- BS degree with 2+ years of applicableexperience, MS degree with 4+ years of applicable experience in electricalengineering, microelectronics.

- Experienced with ASIC design flow,hierarchical physical design strategies, and methodologies and understand deepsub-micron technology issues. Solid knowledge on LP Design, static timinganalysis, EM/IR-Drop/crosstalk analysis, formal verification, physicalverification, DFM. Successful track records of taping out complex, 65/40/28 nmSOC chips.

- Self-motivated, able to workindependently or as a team player, customer focus, accountability, effectivecommunicator, able to coach and provide feedback and develop others

- Excellent verbal and writtencommunication skills in English and project management skills

-Self-initiative, quick learner, eager to learn new technologies

- Good at multi-tasking and prioritysetting

感兴趣可联系我（cissy_pq@163.com）（彭小姐）

小干爹z2z

高速发展， 赞

icfbicfb

MS 4年就是mgr了， 要求不算高，

Cissy_pq

回复 3# icfbicfb


   有需要可联系我哦

toad

唉，么有做过28n的

小力2014

7nm工艺