calibre LVS 求助

zhb19900612 · 发表于 2015-3-31 15:32:44

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cadence LVS 时出现 “
Components with non-identical signal pins ”错误怎么弄，求解决啊！

QQ图片20150331151001.jpg QQ图片20150331152552.png

##################################################

## ##

## C A L I B R E S Y S T E M ##

## ##

## L V S R E P O R T ##

## ##

##################################################

REPORT FILE NAME: vga_pa.lvs.report

LAYOUT NAME: /home/zhb/umc018/vga_pa.sp('vga_pa')

SOURCE NAME: /home/zhb/umc018/vga_pa.src.net('vga_pa')

RULE FILE: /home/zhb/umc018/_G-DF-MIXED_MODE_RFCMOS18-1.8V_3.3V-1P6M-MMC_CALIBRE-LVS-2.1-P2.txt_

RULE FILE TITLE: LVS of UMC 0.18um 1.8V/3.3V 1P6M MMCMixed Mode/RFCMOS Process

CREATION TIME: Tue Mar 31 15:21:10 2015

CURRENT DIRECTORY: /home/zhb/umc018

USER NAME: zhb

CALIBRE VERSION: v2011.3_18.12 Wed Aug 10 15:03:23 PDT 2011

OVERALLCOMPARISON RESULTS

# # #####################

# # # #

# # INCORRECT #

# # # #

# # #####################

Error: Components withnon-identical signal pins.

Warning: Unbalanced smashedmosfets were matched.

**************************************************************************************************************

CELL SUMMARY

**************************************************************************************************************

Result Layout Source

----------- ----------- --------------

CORRECT vga_pa vga_pa

**************************************************************************************************************

LVSPARAMETERS

**************************************************************************************************************

o LVS Setup:

//LVS COMPONENT TYPE PROPERTY

//LVS COMPONENT SUBTYPE PROPERTY

//LVS PIN NAME PROPERTY

LVS POWER NAME "?VDD?" "?VCC?"

LVS GROUND NAME "?VSS?" "?GND?"

LVS CELL SUPPLY NO

LVS RECOGNIZE GATES ALL

LVS IGNORE PORTS NO

LVS CHECK PORT NAMES YES

LVS IGNORE TRIVIAL NAMED PORTS NO

LVS BUILTIN DEVICE PIN SWAP YES

LVS ALL CAPACITOR PINS SWAPPABLE NO

LVS DISCARD PINS BY DEVICE NO

LVS SOFT SUBSTRATE PINS NO

LVS INJECT LOGIC YES

LVS EXPAND UNBALANCED CELLS YES

LVS FLATTEN INSIDE CELL NO

LVS EXPAND SEED PROMOTIONS YES

LVS PRESERVE PARAMETERIZED CELLS NO

LVS GLOBALS ARE PORTS YES

LVS REVERSE WL NO

LVS SPICE PREFER PINS NO

LVS SPICE SLASH IS SPACE YES

LVS SPICE ALLOW FLOATING PINS YES

//LVS SPICE ALLOW INLINE PARAMETERS

LVS SPICE ALLOW UNQUOTED STRINGS NO

LVS SPICE CONDITIONAL LDD NO

LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO

LVS SPICE IMPLIED MOS AREA NO

//LVS SPICE MULTIPLIER NAME

LVS SPICE OVERRIDE GLOBALS NO

LVS SPICE REDEFINE PARAM NO

LVS SPICE REPLICATE DEVICES NO

LVS SPICE SCALE X PARAMETERS NO

LVS SPICE STRICT WL NO

//LVS SPICE OPTION

LVS STRICT SUBTYPES NO

LVS EXACT SUBTYPES NO

LAYOUT CASE YES

SOURCE CASE YES

LVS COMPARE CASE NAMES TYPES SUBTYPES VALUES

LVS DOWNCASE DEVICE NO

LVS REPORT MAXIMUM 50

LVS PROPERTY RESOLUTION MAXIMUM 32

//LVS SIGNATURE MAXIMUM

// LVS FILTER UNUSED OPTION

//LVS REPORT OPTION

LVS REPORT UNITS YES

//LVS NON USER NAME PORT

//LVS NON USER NAME NET

//LVS NON USER NAME INSTANCE

//Reduction

LVS REDUCE SERIES MOS NO

LVS REDUCE PARALLEL MOS YES

LVS REDUCE SEMI SERIES MOS NO

LVS REDUCE SPLIT GATES YES

LVS REDUCE PARALLEL BIPOLAR YES

LVS REDUCE SERIES CAPACITORS YES

LVSREDUCE PARALLEL CAPACITORS YES

LVS REDUCE SERIES RESISTORS YES

LVS REDUCE PARALLEL RESISTORS YES

LVS REDUCE PARALLEL DIODES YES

LVS REDUCTION PRIORITY PARALLEL

LVS SHORT EQUIVALENT NODES NO

//Trace Property

TRACE PROPERTY mn(N_18_G2) l l 7

TRACE PROPERTY mn(N_18_G2) w w 7

TRACE PROPERTY mp(P_18_G2) l l 7

TRACE PROPERTY mp(P_18_G2) w w 7

TRACE PROPERTY mn(N_18_MM) l l 3

TRACE PROPERTY mn(N_18_MM) w w 3

TRACE PROPERTY mp(P_18_MM) l l 3

TRACE PROPERTY mp(P_18_MM) w w 3

TRACE PROPERTY mn(N_LV_18_MM) l l 3

TRACE PROPERTY mn(N_LV_18_MM) w w 3

TRACE PROPERTY mp(P_LV_18_MM) l l 3

TRACE PROPERTY mp(P_LV_18_MM) w w 3

TRACE PROPERTY mn(N_33_G2) l l 3

TRACE PROPERTY mn(N_33_G2) w w 3

TRACE PROPERTY mp(P_33_G2) l l 3

TRACE PROPERTY mp(P_33_G2) w w 3

TRACE PROPERTY mn(N_33_MM) l l 3

TRACE PROPERTY mn(N_33_MM) w w 3

TRACEPROPERTY mp(P_33_MM) l l 3

TRACE PROPERTY mp(P_33_MM) w w 3

TRACE PROPERTY mn(N_LV_33_MM) l l 3

TRACE PROPERTY mn(N_LV_33_MM) w w 3

TRACE PROPERTY mp(P_LV_33_MM) l l 3

TRACE PROPERTY mp(P_LV_33_MM) w w 3

TRACE PROPERTY mn(N_ZERO_18_MM) l l 3

TRACE PROPERTY mn(N_ZERO_18_MM) w w 3

TRACE PROPERTY mn(N_ZERO_33_MM) l l 3

TRACE PROPERTY mn(N_ZERO_33_MM) w w 3

TRACE PROPERTY mn(N_BPW_18_MM) l l 3

TRACE PROPERTY mn(N_BPW_18_MM) w w 3

TRACE PROPERTY mn(N_BPW_33_MM) l l 3

TRACE PROPERTY mn(N_BPW_33_MM) w w 3

TRACE PROPERTY mn(N_PO7W500_18_RF) l l 3

TRACE PROPERTY mn(N_PO7W500_18_RF) w w 3

TRACE PROPERTY mp(P_PO7W500_18_RF) l l 3

TRACE PROPERTY mp(P_PO7W500_18_RF) w w 3

TRACE PROPERTY mn(N_PO7W500_33_RF) l l 3

TRACE PROPERTY mn(N_PO7W500_33_RF) w w 3

TRACE PROPERTY mp(P_PO7W500_33_RF) l l 3

TRACE PROPERTY mp(P_PO7W500_33_RF) w w 3

TRACE PROPERTY mn(N_L18W500_18_RF) l l 3

TRACE PROPERTY mn(N_L18W500_18_RF) w w 3

TRACE PROPERTY mp(P_L18W500_18_RF) l l 3

TRACE PROPERTY mp(P_L18W500_18_RF) w w 3

TRACE PROPERTY mn(N_L34W500_33_RF) l l 3

TRACE PROPERTY mn(N_L34W500_33_RF) w w 3

TRACE PROPERTY mp(P_L34W500_33_RF) l l 3

TRACE PROPERTY mp(P_L34W500_33_RF) w w 3

TRACE PROPERTY mn(N_PG400_G2) l l 3

TRACE PROPERTY mn(N_PG400_G2) w w 3

TRACE PROPERTY mn(N_PD400_G2) l l 3

TRACE PROPERTY mn(N_PD400_G2) w w 3

TRACE PROPERTY mp(P_L400_G2) l l 3

TRACE PROPERTY mp(P_L400_G2) w w 3

TRACE PROPERTY mn(N_PG1020_G2) l l 3

TRACE PROPERTY mn(N_PG1020_G2) w w 3

TRACE PROPERTY mn(N_PD1020_G2) l l 3

TRACE PROPERTY mn(N_PD1020_G2) w w 3

TRACE PROPERTY mp(P_L1020_G2) l l 3

TRACE PROPERTY mp(P_L1020_G2) w w 3

TRACE PROPERTY c(VARMIS_18_RF) nf nf 3

TRACE PROPERTY c(VARDIOP_RF) nf nf 3

TRACE PROPERTY r(RSNWELL) r r 3

TRACE PROPERTY r(RSND) r r 3

TRACE PROPERTY r(RSPD) r r 3

TRACE PROPERTY r(RSNPO) r r 3

TRACE PROPERTY r(RSPPO) r r 3

TRACE PROPERTY r(RNND_MM) r r 3

TRACE PROPERTY r(RNPD) r r 3

TRACE PROPERTY r(RNNPO) r r 29

TRACE PROPERTY r(RNNPO_MM) r r 3

TRACE PROPERTY r(RNNPO_RF) r r 3

TRACE PROPERTY r(RNPPO) r r 66

TRACE PROPERTY r(RNPPO_MM) r r 3

TRACE PROPERTY r(RNPPO_RF) r r 3

TRACE PROPERTY r(RNHR1000_MM) r r 3

TRACE PROPERTY r(RNHR_RF) r r 3

TRACE PROPERTY r(RM1_MM) r r 3

TRACE PROPERTY r(RM2_MM) r r 3

TRACE PROPERTY r(RM3_MM) r r 3

TRACE PROPERTY r(RM4_MM) r r 3

TRACE PROPERTY r(RM5_MM) r r 3

TRACE PROPERTY r(RM6_MM) r r 3

TRACE PROPERTY d(DION_G2) p p 3

TRACE PROPERTY d(DION_G2) a a 3

TRACE PROPERTY d(DIOP_G2) a a 3

TRACE PROPERTY d(DIOP_G2) p p 3

TRACE PROPERTY d(DIONW_G2) a a 3

TRACE PROPERTY d(DIONW_G2) p p 3

TRACE PROPERTY d(DION_MM) a a 3

TRACE PROPERTY d(DION_MM) p p 3

TRACE PROPERTY d(DIOP_MM) a a 3

TRACE PROPERTY d(DIOP_MM) p p 3

TRACE PROPERTY d(DIONW_MM) a a 3

TRACEPROPERTY d(DIONW_MM) p p 3

TRACE PROPERTY q(PNP_V50X50_G2) a a 3

TRACE PROPERTY q(PNP_V100X100_G2) a a 3

TRACE PROPERTY q(PNP_V50X50_MM) a a 3

TRACE PROPERTY q(PNP_V100X100_MM) a a 3

TRACE PROPERTY c(MIMCAPS_MM) c c 3

TRACEPROPERTY c(MIMCAPM_RF) c c 3

TRACE PROPERTY l(L_SLCR20K_RF) d d 3

TRACE PROPERTY l(L_SLCR20K_RF) n n 3

TRACE PROPERTY l(L_SLCR20K_RF) w w 3

COMPONENT TYPES WITH NON-IDENTICAL SIGNALPINS

**************************************************************************************************************

(Cells with the same ( or corresponding ) name that have differentsignal

pin names are listed below. Pinsthat do not appear in all corresponding

cells in both source and layout are ignored by the comparisonalgorithm.)

Layout Component Type: R (3 pins): (p n) sub

Layout Extra Pins: sub

Layout Component Type: R (2 pins): (p n)

No Extra Pins.

Source Component Type: R (3 pins): (p n) sub

Source Extra Pins: sub

CELL COMPARISON RESULTS (TOP LEVEL )

# ################### _ _

# # # * *

# # # CORRECT # |

# # # # \___/

# ###################

Warning: Unbalanced smashedmosfets were matched.

LAYOUT CELL NAME: vga_pa

SOURCE CELL NAME: vga_pa

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS

--------------------------

Layout Source Component Type

------ ------ --------------

Ports: 10 10

Nets: 70 29 *

Instances: 228 15 * MN (4 pins)

10 10 C (2 pins): p n

8 8 C (3 pins): p n sub

6 6 R (2 pins)

28 12 * D (2 pins)

1 1 L (3 pins)

------ ------

Total Inst: 281 52

NUMBERS OF OBJECTS AFTER TRANSFORMATION

---------------------------------------

Layout Source Component Type

------ ------ --------------

Ports: 10 10

Nets: 22 22

Instances: 3 3 MN (4 pins)

10 10 C (2 pins): p n

4 4 C (3 pins): p n sub

6 6 R (2 pins)

12 12 D (2 pins)

1 1 L (3 pins)

4 4 _smn2v (4 pins)

------ ------

Total Inst: 40 40

* = Number of objects in layout different from number in source.

**************************************************************************************************************

INFORMATION ANDWARNINGS

**************************************************************************************************************

Matched Matched Unmatched Unmatched Component

Layout Source Layout Source Type

------- ------- --------- --------- ---------

Ports: 10 10 0 0

Nets: 22 22 0 0

Instances: 2 2 0 0 MN(N_18_MM)

1 1 0 0 MN(N_33_MM)

10 10 0 0 C(PAD_RF)

4 4 0 0 C(MIMCAPM_RF)

2 2 0 0 R(RNHR1000_MM)

4 4 0 0 R(RNND_MM)

12 12 0 0 D(DIOP_MM)

1 1 0 0 L(L_SLCR20K_RF)

4 4 0 0 _smn2v

------- ------- --------- ---------

Total Inst: 40 40 0 0

o Statistics:

228 layout mos transistors were reduced to11. 44 connecting nets were deleted.

129 mos transistors were deleted by parallel reduction.

88 mos transistors and 44 connecting nets were deleted by split-gatereduction.

6source mos transistors were reduced to 2. 2 connecting nets were deleted.

4 mos transistors and 2 connecting nets were deleted by split-gatereduction.

7parallel layout capacitors were reduced to 3.

7parallel source capacitors were reduced to 3.

20parallel layout diodes were reduced to 4.

1source net had all its pins removed and was deleted.

o Initial Correspondence Points:

Ports: V_ctr1 V_ctr2 V_ctr3gnd vdd33 vdd18 L1 L4 vin vout

o Matched Mosfets Which Have Been UnequallyReduced:

X101/M28(859.450,425.850) MM6

X101/M29(859.450,424.470) MM2

X99/M0(859.450,329.990) MM4

X99/M1(859.450,328.610) ** missing smashedmosfet **

X99/M2(859.450,327.230) ** missingsmashed mosfet **

X99/M3(859.450,325.850) ** missingsmashed mosfet **

X99/M4(859.450,324.470) ** missingsmashed mosfet **

X99/M5(859.450,323.090) ** missingsmashed mosfet **

X99/M6(859.450,321.710) ** missingsmashed mosfet **

X99/M7(859.450,320.330) ** missingsmashed mosfet **

X99/M8(859.450,318.950) ** missingsmashed mosfet **

X99/M9(859.450,317.570) ** missing smashed mosfet **

X99/M10(859.450,316.190) ** missingsmashed mosfet **

X99/M11(859.450,314.810) ** missingsmashed mosfet **

X99/M12(859.450,313.430) ** missingsmashed mosfet **

X99/M13(859.450,312.050) ** missingsmashed mosfet **

X99/M14(859.450,310.670) ** missingsmashed mosfet **

X99/M15(859.450,309.290) ** missingsmashed mosfet **

X99/M16(859.450,307.910) ** missingsmashed mosfet **

X99/M17(859.450,306.530) ** missingsmashed mosfet **

X99/M18(859.450,305.150) ** missingsmashed mosfet **

X99/M19(859.450,303.770) ** missingsmashed mosfet **

X99/M20(859.450,302.390) ** missingsmashed mosfet **

X99/M21(859.450,301.010) ** missingsmashed mosfet **

X99/M22(859.450,299.630) ** missingsmashed mosfet **

X99/M23(859.450,298.250) ** missingsmashed mosfet **

X99/M24(859.450,296.870) ** missingsmashed mosfet **

X99/M25(859.450,295.490) ** missing smashed mosfet **

X99/M26(859.450,294.110) ** missingsmashed mosfet **

X99/M27(859.450,292.730) ** missingsmashed mosfet **

X99/M28(859.450,291.350) ** missingsmashed mosfet **

X99/M29(859.450,289.970) ** missingsmashed mosfet **

X100/M0(859.450,396.390) ** missingsmashed mosfet **

X100/M1(859.450,395.010) ** missingsmashed mosfet **

X100/M2(859.450,393.630) ** missingsmashed mosfet **

X100/M3(859.450,392.250) ** missing smashed mosfet **

X100/M4(859.450,390.870) ** missingsmashed mosfet **

X100/M5(859.450,389.490) ** missingsmashed mosfet **

X100/M6(859.450,388.110) ** missingsmashed mosfet **

X100/M7(859.450,386.730) ** missingsmashed mosfet **

X100/M8(859.450,385.350) ** missingsmashed mosfet **

X100/M9(859.450,383.970) ** missingsmashed mosfet **

X100/M10(859.450,382.590) ** missingsmashed mosfet **

X100/M11(859.450,381.210) ** missingsmashed mosfet **

X100/M12(859.450,379.830) ** missingsmashed mosfet **

X100/M13(859.450,378.450) ** missingsmashed mosfet **

X100/M14(859.450,377.070) ** missing smashedmosfet **

X100/M15(859.450,375.690) ** missingsmashed mosfet **

X100/M16(859.450,374.310) ** missingsmashed mosfet **

X100/M17(859.450,372.930) ** missingsmashed mosfet **

X100/M18(859.450,371.550) ** missingsmashed mosfet **

X100/M19(859.450,370.170) ** missingsmashed mosfet **

X100/M20(859.450,368.790) ** missingsmashed mosfet **

X102/M27(907.090,425.850) MM7

X102/M28(907.090,424.470) MM1

X102/M29(907.090,423.090) MM3

X103/M0(907.100,328.610) ** missingsmashed mosfet **

X103/M1(907.100,327.230) ** missingsmashed mosfet **

X103/M2(907.100,325.850) ** missingsmashed mosfet **

X103/M3(907.100,324.470) ** missingsmashed mosfet **

X103/M4(907.100,323.090) ** missingsmashed mosfet **

X103/M5(907.100,321.710) ** missingsmashed mosfet **

X103/M6(907.100,320.330) ** missingsmashed mosfet **

X103/M7(907.100,318.950) ** missingsmashed mosfet **

X103/M8(907.100,317.570) ** missingsmashed mosfet **

X103/M9(907.100,316.190) ** missingsmashed mosfet **

X103/M10(907.100,314.810) ** missingsmashed mosfet **

X103/M11(907.100,313.430) ** missingsmashed mosfet **

X103/M12(907.100,312.050) ** missingsmashed mosfet **

X103/M13(907.100,310.670) ** missingsmashed mosfet **

X103/M14(907.100,309.290) ** missingsmashed mosfet **

X103/M15(907.100,307.910) ** missingsmashed mosfet **

X103/M16(907.100,306.530) ** missingsmashed mosfet **

X103/M17(907.100,305.150) ** missing smashed mosfet **

X103/M18(907.100,303.770) ** missingsmashed mosfet **

X103/M19(907.100,302.390) ** missingsmashed mosfet **

X103/M20(907.100,301.010) ** missingsmashed mosfet **

X103/M21(907.100,299.630) ** missingsmashed mosfet **

X103/M22(907.100,298.250) ** missingsmashed mosfet **

X103/M23(907.100,296.870) ** missingsmashed mosfet **

X103/M24(907.100,295.490) ** missingsmashed mosfet **

X103/M25(907.100,294.110) ** missingsmashed mosfet **

X103/M26(907.100,292.730) ** missingsmashed mosfet **

X103/M27(907.100,291.350) ** missingsmashed mosfet **

X103/M28(907.100,289.970) ** missingsmashed mosfet **

X103/M29(907.100,288.590) ** missingsmashed mosfet **

X104/M0(907.100,395.010) ** missing smashed mosfet **

X104/M1(907.100,393.630) ** missingsmashed mosfet **

X104/M2(907.100,392.250) ** missingsmashed mosfet **

X104/M3(907.100,390.870) ** missingsmashed mosfet **

X104/M4(907.100,389.490) ** missingsmashed mosfet **

X104/M5(907.100,388.110) ** missingsmashed mosfet **

X104/M6(907.100,386.730) ** missingsmashed mosfet **

X104/M7(907.100,385.350) ** missingsmashed mosfet **

X104/M8(907.100,383.970) ** missing smashed mosfet **

X104/M9(907.100,382.590) ** missingsmashed mosfet **

X104/M10(907.100,381.210) ** missingsmashed mosfet **

X104/M11(907.100,379.830) ** missingsmashed mosfet **

X104/M12(907.100,378.450) ** missingsmashed mosfet **

X104/M13(907.100,377.070) ** missingsmashed mosfet **

X104/M14(907.100,375.690) ** missingsmashed mosfet **

X104/M15(907.100,374.310) ** missingsmashed mosfet **

X104/M16(907.100,372.930) ** missingsmashed mosfet **

X104/M17(907.100,371.550) ** missingsmashed mosfet **

X104/M18(907.100,370.170) ** missingsmashed mosfet **

X104/M19(907.100,368.790) ** missing smashedmosfet **

**************************************************************************************************************

SUMMARY

**************************************************************************************************************

Total CPU Time: 0 sec

Total Elapsed Time: 0 sec

poo4555656 · 发表于 2015-3-31 16:44:43

对于第一张图我刚好前两天出过是没有定义电源地
在LVS的option中把电源地加进去

motofatfat · 发表于 2015-3-31 16:55:00

看不出花樣可能有接錯

supericeman999 · 发表于 2015-3-31 17:03:44

電阻的部分calibre 認為他有三隻腳而spice只定義兩隻
把spice 的部分改為三隻腳就行了!!

gaozhiqiang · 发表于 2015-3-31 19:35:31

可能电路端口标识层没填写

wzc92 · 发表于 2015-4-1 09:13:48

只能排除法了。结合楼上各位大神，总结一下：1、先看网表电阻定义是否符合你的原理图。2、看电源等在规则文件是否有定义 3、是否有短路、开路等相关问题 4、机器、服务器异常，重启。暂先这么多~

alice_xyf · 发表于 2015-4-1 09:25:06

电阻在版图中有2端，也有3端的画法，但是netlist 中认得是三端。

supericeman999 · 发表于 2015-4-1 11:07:32

所以就看你是要改spice的定義還是要去改LVS command file
我個人比較常用前面的方法
比較簡單

zhb19900612 · 发表于 2015-4-1 11:23:17

回复 2# poo4555656

双电源怎么添加啊

zhb19900612 · 发表于 2015-4-1 11:26:28

回复 8# supericeman999

应该不用去改，自动匹配的！calibre是集成在cadence里的，会自动匹配。

[求助] calibre LVS 求助

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