上海需要一位 CAD

KT咨询-IC电子

【猎头职位：上海需要一位  CAD】联系人：Raymond-Chen 邮箱：hr@kthr.com，微信也可查询职位啦！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！
Responsibilities:  
1. Develop verification environment, including test bench and regression system creation, embed it in company customized design flow
2. Build test plan and verify the function of design, support gate level functional verification, run coverage and regression. Analyze coverage gaps and devise strategy to fill coverage holes
3. Work closely with different groups to review specification, improve verification plan and methodology, and ensure full test coverage
4. Interfacing EDA vendors for tools' evaluation, assess vendors' design verification capabilities and convergence
5. CAD related documentation.


Requirements:
1. BSEE with 5+ (or MSEE with 3+) years experience in ASIC verification, complex SOC verification experience is preferred.
2. Solid knowledge in verification methodology. Experience in verification using random stimulus along with functional coverage and assertion-based verification method. Experience in UVM/OVM, object oriented design principles, Mentor Questasim SV, lower power verification flow with CPF/UPF.
3. Experience in developing block and chip level test benches, test plan creation.
4. Good at timing analysis, practical skill with gate-level simulation and debugging techniques.
5. Familiar with frontend EDA tools used in all phases of the frontend design cycle (such as NC, RC, Conformal, ETS form Cadence; Or VCS, DC, Formality, PT from Synopsys) is a plus.
6. Strong script programming skills, such as Shell scripting, Perl and Tcl programming, to develop command scripts.
7. Self-motivated to drive for excellence. Must be a team player, and be disciplined and well organized.
8. Excellent communication skills, and be able to work under schedule pressure.

magictracyguy

后端的cad要么

spauls

Still open ?