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Description: - RTL design and verification for the embedded CPU subsystem in the wireless baseband ASIC
- RTL design and verification associated with top-level/centralized blocks and integration of third-party/in-house IPs (e.g., PCIe/SDIO/USB/ARM/ARC)
- Chip-level methodology (clocks, resets, test planning)
- Synthesis/STA/LEC/DFT implementation
- FPGA prototyping
- Silicon Validation
Familiarity with embedded CPUs (ARM/CEVA), PCIe, SDIO, USB, SATA, MIPI interface protocol would be a big plus.
Required Skills: - BSEE with 6+ years, MSEE with 4+ years of experience, or equivalent combination of education and experience.
- Prior experience with subsystems built around embedded processors (CEVA/ARM) would be highly desirable
- Hands on experience on synthesis/STA/LEC/DFT would be highly desirable
- FPGA emulation/debug experience would be desirable
- Well organized, methodical, and detail oriented
- Must be a team player and easy to work with
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发表于 2016-3-25 16:09:43
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