formality sytemveirlogRTL/netlist的一个问题

sino_crane

各位好，

   之前没有做过SV RTL formal check,有以下问题，不能link，哪位大虾能解答一下。谢谢啦

Information: Created design named 'invmod_gen_I_rmult_ifp_r_mult_inf_master_DATA_BW_16_ADDR_BW_17_I_div_ifp_div_inf_master_DI0_BW_10_DI1_BW_10_I_mem_ifp_intlv_mem_arb_inf_master_DD_BW_31_DR_BW_12_I_invmod_ifp_invmod_inf_gen_'. (FE-LINK-13)
Status:   Elaborating design interleaver_arith   ...  
Information: Created design named 'interleaver_arith_I_mem_arb_ifp_intlv_mem_s_inf_slave_numAgent_5_DATA_BW_16_ADDR_BW_17_I_intlv_mem_ifp_sram_sp_inf_ctrl_DATA_BW_16_ADDR_BW_17_I_rmult0_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult1_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult2_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_20_DI1_BW_10_I_div_ifp_div_s_inf_slave_numAgent_5_DD_BW_31_DR_BW_12_'. (FE-LINK-13)
Status:   Elaborating design mem_ctrl_intlv  DATA_BW=16, ADDR_BW=17, numAgent=5 ...  
Information: Created design named 'mem_ctrl_intlv_DATA_BW16_ADDR_BW17_numAgent5_I_mem_arb_ifp_intlv_mem_s_inf_ctrl_DATA_BW_16_ADDR_BW_17_I_intlv_mem_ifp_sram_sp_inf_slave_numAgent_5_DATA_BW_16_ADDR_BW_17_'. (FE-LINK-13)
Status:   Elaborating design rmult_intlv  numAgent=2, RMUL_DI0_BW=10, RMUL_DI1_BW=10 ...  
Information: Created design named 'rmult_intlv_numAgent2_RMUL_DI0_BW10_RMUL_DI1_BW10_I_rmult_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_'. (FE-LINK-13)
Status:   Elaborating design rmult_intlv  numAgent=2, RMUL_DI0_BW=20, RMUL_DI1_BW=10 ...  
Information: Created design named 'rmult_intlv_numAgent2_RMUL_DI0_BW20_RMUL_DI1_BW10_I_rmult_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_20_DI1_BW_10_'. (FE-LINK-13)
Status:   Elaborating design div_intlv  numAgent=5, DIV_DD_BW=31, DIV_DR_BW=12, DIV_BIT_CYC=4, NUM_DIV_CYC=8 ...  
Information: Created design named 'div_intlv_numAgent5_DIV_DD_BW31_DIV_DR_BW12_DIV_BIT_CYC4_NUM_DIV_CYC8_I_div_ifp_div_s_inf_slave_numAgent_5_DD_BW_31_DR_BW_12_I_div_nb_ifp_divnb_m_inf_master_CYC_BIT_4_DR_BW_12_NUM_STEP_8_'. (FE-LINK-13)
Warning: Cannot link cell '/WORK/interleaver_arith_I_mem_arb_ifp_intlv_mem_s_inf_slave_numAgent_5_DATA_BW_16_ADDR_BW_17_I_intlv_mem_ifp_sram_sp_inf_ctrl_DATA_BW_16_ADDR_BW_17_I_rmult0_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult1_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult2_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_20_DI1_BW_10_I_div_ifp_div_s_inf_slave_numAgent_5_DD_BW_31_DR_BW_12_/div_nb_per_cyc[7].div_nb' to its reference design 'div_nb'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/interleaver_arith_I_mem_arb_ifp_intlv_mem_s_inf_slave_numAgent_5_DATA_BW_16_ADDR_BW_17_I_intlv_mem_ifp_sram_sp_inf_ctrl_DATA_BW_16_ADDR_BW_17_I_rmult0_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult1_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult2_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_20_DI1_BW_10_I_div_ifp_div_s_inf_slave_numAgent_5_DD_BW_31_DR_BW_12_/div_nb_per_cyc[6].div_nb' to its reference design 'div_nb'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/interleaver_arith_I_mem_arb_ifp_intlv_mem_s_inf_slave_numAgent_5_DATA_BW_16_ADDR_BW_17_I_intlv_mem_ifp_sram_sp_inf_ctrl_DATA_BW_16_ADDR_BW_17_I_rmult0_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult1_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult2_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_20_DI1_BW_10_I_div_ifp_div_s_inf_slave_numAgent_5_DD_BW_31_DR_BW_12_/div_nb_per_cyc[5].div_nb' to its reference design 'div_nb'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/interleaver_arith_I_mem_arb_ifp_intlv_mem_s_inf_slave_numAgent_5_DATA_BW_16_ADDR_BW_17_I_intlv_mem_ifp_sram_sp_inf_ctrl_DATA_BW_16_ADDR_BW_17_I_rmult0_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult1_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult2_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_20_DI1_BW_10_I_div_ifp_div_s_inf_slave_numAgent_5_DD_BW_31_DR_BW_12_/div_nb_per_cyc[4].div_nb' to its reference design 'div_nb'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/interleaver_arith_I_mem_arb_ifp_intlv_mem_s_inf_slave_numAgent_5_DATA_BW_16_ADDR_BW_17_I_intlv_mem_ifp_sram_sp_inf_ctrl_DATA_BW_16_ADDR_BW_17_I_rmult0_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult1_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult2_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_20_DI1_BW_10_I_div_ifp_div_s_inf_slave_numAgent_5_DD_BW_31_DR_BW_12_/div_nb_per_cyc[3].div_nb' to its reference design 'div_nb'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/interleaver_arith_I_mem_arb_ifp_intlv_mem_s_inf_slave_numAgent_5_DATA_BW_16_ADDR_BW_17_I_intlv_mem_ifp_sram_sp_inf_ctrl_DATA_BW_16_ADDR_BW_17_I_rmult0_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult1_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult2_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_20_DI1_BW_10_I_div_ifp_div_s_inf_slave_numAgent_5_DD_BW_31_DR_BW_12_/div_nb_per_cyc[2].div_nb' to its reference design 'div_nb'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/interleaver_arith_I_mem_arb_ifp_intlv_mem_s_inf_slave_numAgent_5_DATA_BW_16_ADDR_BW_17_I_intlv_mem_ifp_sram_sp_inf_ctrl_DATA_BW_16_ADDR_BW_17_I_rmult0_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult1_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult2_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_20_DI1_BW_10_I_div_ifp_div_s_inf_slave_numAgent_5_DD_BW_31_DR_BW_12_/div_nb_per_cyc[1].div_nb' to its reference design 'div_nb'. (FE-LINK-2)
Warning: Cannot link cell '/WORK/interleaver_arith_I_mem_arb_ifp_intlv_mem_s_inf_slave_numAgent_5_DATA_BW_16_ADDR_BW_17_I_intlv_mem_ifp_sram_sp_inf_ctrl_DATA_BW_16_ADDR_BW_17_I_rmult0_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult1_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_10_DI1_BW_10_I_rmult2_ifp_rmult_s_inf_slave_numAgent_2_DI0_BW_20_DI1_BW_10_I_div_ifp_div_s_inf_slave_numAgent_5_DD_BW_31_DR_BW_12_/div_nb_per_cyc[0].div_nb' to its reference design 'div_nb'. (FE-LINK-2)
Error: Unresolved references detected during link. (FM-234)
Error: Failed to set top design to 'r:/WORK/interleaver_wrap' (FM-156)