dc 综合时候的一个问题

fresh116

source ../scripts/jsq.tcl
Using operating conditions 'ss_1v62_125c' found in library 'ss_1v62_125c'.
Using operating conditions 'ff_1v98_m40c' found in library 'ff_1v98_m40c'.
Running PRESTO HDLC
Searching for ../verilog/jsq.v
Searching for ../verilog/b2d.v_sel542
Searching for ../smic18m_library/b2d.v_sel542
Searching for ./b2d.v_sel542
Searching for /tools/synopsys/dc1109/libraries/syn/b2d.v_sel542
Searching for /tools/synopsys/dc1109/minpower/syn/b2d.v_sel542
Searching for /tools/synopsys/dc1109/dw/syn_ver/b2d.v_sel542
Searching for /tools/synopsys/dc1109/dw/sim_ver/b2d.v_sel542
Error:  Unable to open file `b2d.v_sel542': in search_path {../verilog ../smic18m_library . /tools/synopsys/dc1109/libraries/syn /tools/synopsys/dc1109/minpower/syn /tools/synopsys/dc1109/dw/syn_ver /tools/synopsys/dc1109/dw/sim_ver}. (VER-41)
*** Presto compilation terminated with 1 errors. ***




搜索不到b2d.v_sel542，但是我的源文件是 b2d.v,脚本也没写搜这个文件，这个问题不是每次都出现，但是出现的时候 b2d.v_sel后面的数字都不一样。不知道是什么原因导致的，是软件bug吗?还是我自己没写清楚。






下面是部分的脚本


：reset_design


set search_path "../verilog ../smic18m_library $search_path "
set target_library  {ss_1v62_125c.db}
set synthetic_library [list standard.sldb dw_foundation.sldb]
set link_library [concat  "*" $target_library $synthetic_library ff_1v98_m40c.db]
set symbol_library  {smic18m.sdb }


set high_fanout_net_threshold 2000
set hdlin_auto_save_templates true  
set compile_auto_ungroup_count_leaf_cells true
set compile_auto_ungroup_override_wlm true
set hdlin_keep_signal_name all


#********************************************************************                                                


set myFiles [list jsq.v b2d.v ]
set fileFormat verilog              ;# verilog or VHDL
set basename jsq                    ;# Top-level module name
set myClk clk                       ;# The name of your clock
#set myClk2 clk_spi
set virtual 0                       ;# 1 if virtual clock, 0 if real clock

keppel7000

你可以把analysis + elaborate的写法换成read_verilog试试看。不一定对。

Andy126