Vias between layers in CADENCE and TSMC PDK

Ryan67

Hi,

  I'm new in Cadence and I'm designing circuits with TSMC0.13umPDK. My circuit contains 8 layers, but I don't know; how to place a via betweentwo layers? for example metal via between met1 and met2.

  I'm trying to do this in schematic, may be this is notpossible in the schematic? because in the vias folder of my KitDesign TSMC90nm thereare only symbolic and layout folders? if this is correct in which step, we canadd vias between layers and via_gnd to take their influence in the performanceof the designed circuits (during simulation with cadence).

  I will appreciate your help.

podcast

Basically you can't include the effect of via during the schematic simulation. You need to layout the circuit and do extraction so you can get the via resistance. If you want to learn IC design, I suggest you to learn with someone who have some experience. Otherwise you will waste a lot of time.

Ryan67

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Thanks for your help.

saintpeter

呵呵

satish_acad

thansk