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楼主 |
发表于 2014-12-12 09:59:03
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回复 2# x_gate
我尝试用了级联,如下:
clk_ctrl_4_to_1 clk_ctrl_4_to_1_u0 (
.clkselect (clkselect_0),
.inclk0x (clk_in_0),
.inclk1x (clk_in_1),
.inclk2x (1'b0),
.inclk3x (1'b0),
.outclk (clk_out_0)
);
clk_ctrl_4_to_1 clk_ctrl_4_to_1_u1 (
.clkselect (clkselect_1),
.inclk0x (clk_in_2),
.inclk1x (clk_in_3),
.inclk2x (1'b0),
.inclk3x (1'b0),
.outclk (clk_out_1)
);
clk_ctrl_4_to_1 clk_ctrl_4_to_1_u2 (
.clkselect (clkselect_2),
.inclk0x (clk_out_0),
.inclk1x (clk_out_1),
.inclk2x (1'b0),
.inclk3x (1'b0),
.outclk (clk_out)
);
但是会报错:
Error (15836): inclk[0] port of Clock Select Block "clk_ctrl_4_to_1:clk_ctrl_4_to_1_u2|clk_ctrl_4_to_1_altclkctrl_3ji:clk_ctrl_4_to_1_altclkctrl_3ji_component|sd2" is driven by an illegal source, but must be driven by a clock pin or a PLL's CLK or FBOUT output
Info (15024): Input port INCLK[0] of node "clk_ctrl_4_to_1:clk_ctrl_4_to_1_u2|clk_ctrl_4_to_1_altclkctrl_3ji:clk_ctrl_4_to_1_altclkctrl_3ji_component|sd2" is driven by clk_ctrl_4_to_1:clk_ctrl_4_to_1_u0|clk_ctrl_4_to_1_altclkctrl_3ji:clk_ctrl_4_to_1_altclkctrl_3ji_component|wire_sd1_outclk which is OUTCLK output port of Clock enable block type node clk_ctrl_4_to_1:clk_ctrl_4_to_1_u0|clk_ctrl_4_to_1_altclkctrl_3ji:clk_ctrl_4_to_1_altclkctrl_3ji_component|sd1
不知道该怎么级联了。 |
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