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处理视频图像,使用xilinx v5的板子,当964*625的相机输出,有效像素区域768*576,,,发现使用下面的代码之后,每次program,板子输出的视频有行列的偏差,每次都不一样。
求问,如何使用自己计数器使板子输出和不经过板子时一致。(如果直接对lval fval cameralink 使用wire assign定义则能满足)
附代码:
module cameralink(
clk,
rst_n,
fval,
lval,
// dval,
cameralink_A,
clk_out,
fval_out,
lval_out,
cameralink_B
);
input clk;
input rst_n;
input fval;
input lval;
// input dval;
input [7:0]cameralink_A;
output clk_out;
output fval_out;
output lval_out;
output cameralink_B;
wire clk_out;
assign clk_out=clk;
reg [7:0] video_in_data_r;
reg [7:0] video_out_data_r;
/*************************计数解码模块*********************************/
reg [9:0] pix_in_x_cnt; //964个,8+ 768+ 188 一行有768个像素
reg [9:0] pix_in_y_cnt; //625个,11+ 576+ 38 一帧有576行像素
//fval 第29行至600行为1,其余为0,一帧共625行
//lval 第20列至842列为1,其余为0,一行共964行
always @ (posedge clk )begin
if(!rst_n)
pix_in_x_cnt <= 10'd0;
else begin
if(pix_in_x_cnt == 10'd964)
pix_in_x_cnt <= 10'd0;
else
pix_in_x_cnt <= pix_in_x_cnt+1'b1;
end
end
always @ (posedge clk )begin
if(!rst_n)
pix_in_y_cnt <= 10'd0;
else begin
if(pix_in_y_cnt == 10'd625)
pix_in_y_cnt <= 10'd0;
else begin
if(pix_in_x_cnt == 10'd964)
pix_in_y_cnt <= pix_in_y_cnt+1'b1;
end
end
end
wire dval; //有效像素区域
assign dval=((pix_in_x_cnt>=10'd27)&&(pix_in_x_cnt<=10'd794))&&((pix_in_y_cnt>=10'd33)&&(pix_in_y_cnt<=10'd608));
always @ (posedge clk )begin
if(!rst_n)begin
video_in_data_r<=8'd0;
end
else begin
if(dval)begin
video_in_data_r<=cameralink_A;
end
end
end
/*************************算法处理模块*********************************/
/*************************计数编码模块*********************************/
reg [9:0] pix_out_x_cnt; //964个,8+ 768+ 188 一行有768个像素
reg [9:0] pix_out_y_cnt; //625个,11+ 576+ 38 一帧有576行像素
//fval 第29行至620行为1,其余为0,一帧共625行
//lval 第20列至842列为1,其余为0,一行共964行
wire frame_end_flag;
assign frame_end_flag=((pix_in_x_cnt == 10'd0)&&(pix_in_y_cnt == 10'd0));
always @ (posedge clk)begin
if(!rst_n)
pix_out_x_cnt <= 10'd0;
else begin
if((pix_out_x_cnt == 10'd964)|| (frame_end_flag))
pix_out_x_cnt <= 10'd0;
else
pix_out_x_cnt <= pix_out_x_cnt+1'b1;
end
end
always @ (posedge clk )begin
if(!rst_n)
pix_out_y_cnt <= 10'd0;
else begin
if((pix_out_y_cnt == 10'd625)|| (frame_end_flag))
pix_out_y_cnt <= 10'd0;
else if(pix_out_x_cnt == 10'd964)
pix_out_y_cnt <= pix_out_y_cnt+1'b1;
end
end
wire fval_out;
assign fval_out=((pix_out_y_cnt>=10'd28)&&(pix_out_y_cnt<=10'd619));//初始
// assign fval_out=fval;
wire lval_out;
assign lval_out=((pix_out_x_cnt>=10'd19)&&(pix_out_x_cnt<=10'd841));
// assign lval_out=lval;
wire pix_en_dis; //有效像素区域
assign pix_en_dis=((pix_out_x_cnt>=10'd27)&&(pix_out_x_cnt<=10'd794))&&((pix_out_y_cnt>=10'd33)&&(pix_out_y_cnt<=10'd608));
wire [7:0] cameralink_B;
reg [7:0] cameralink_B_r;
assign cameralink_B=cameralink_B_r;
always @ (posedge clk )begin
if(!rst_n)
begin
cameralink_B_r<=8'd0;
end
else begin
if(pix_en_dis)
begin
//cameralink_B_r<=video_out_data_r;
cameralink_B_r<=video_in_data_r;
end
else
cameralink_B_r<=8'd0;
end
end
endmodule |
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