初学FPGA 编译时出现很多警告 求指点

IC.Michael

初学FPGA，写了个简单的counter，下载到板子上，compilation的时候报了25个警告，不知道是否严重。还请论坛里的朋友指一下方向，谢谢啦！
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (332087): The master clock for this clock assignment could not be derived.  Clock: inst1|altpll_component|auto_generated|pll1|clk[0] was not created.

Warning (332035): No clocks found on or feeding the specified source node: inst1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:

Warning (332056): Node: inst1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock CLOCK_50 is never referenced in any input or output delay assignment.
Warning (332087): The master clock for this clock assignment could not be derived.  Clock: inst1|altpll_component|auto_generated|pll1|clk[0] was not created.

Warning (332035): No clocks found on or feeding the specified source node: inst1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:

Warning (332056): Node: inst1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock CLOCK_50 is never referenced in any input or output delay assignment.
Warning (332087): The master clock for this clock assignment could not be derived.  Clock: inst1|altpll_component|auto_generated|pll1|clk[0] was not created.

Warning (332035): No clocks found on or feeding the specified source node: inst1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:

Warning (332056): Node: inst1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock CLOCK_50 is never referenced in any input or output delay assignment.
Warning (332087): The master clock for this clock assignment could not be derived.  Clock: inst1|altpll_component|auto_generated|pll1|clk[0] was not created.

Warning (332035): No clocks found on or feeding the specified source node: inst1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:

Warning (332056): Node: inst1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock CLOCK_50 is never referenced in any input or output delay assignment.

a254591139

非常高那些LZ 的好东西啊

IC.Michael

回复 2# a254591139


   仁兄 你这是。。。

chenchu0910

截图比这样好，这样根本没有兴趣看下去，等于浪费时间

IC.Michael

回复 4# chenchu0910


   最右边有一小部分截图截不全了。。。

acgoal

建议你最好先仿真过，哪怕一个比较简单的仿真代码，看起来有时钟没有生成。从这个log不能一眼看出来是否影响功能。

IC.Michael

回复 6# acgoal


   恩恩 我再去仔细看看。我仿真的是DE2-115附带的一个my_first_FPGA 点亮LED灯的一个实验。

panlei_wh

回复 1# IC.Michael


    你好，我看了你这个告警，你这个应该主要报的是PLL的告警，原因有两点，第一可能是PLL的输入时钟管脚绑定不合理，时钟有专门的引脚；第二点可能是PLL的设置有问题，或者是没有约束文件。因为看不到你的实际情况，所以只是提供一个建议，你再看看，好吧。

IC.Michael

回复 8# panlei_wh


   谢谢你的回复，非常感谢，我再继续看看。PLL我是按照教程里面用MegaWizard Plug-In Manager设置的。

jiegeng66

回复 9# IC.Michael
先从书上面的例子仿真书上基本没错自己编写你得学到什么时候啊，找到学习方法远比刻苦努力来得快