初学FPGA，写了个简单的counter，下载到板子上，compilation的时候报了25个警告，不知道是否严重。还请论坛里的朋友指一下方向，谢谢啦！
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (332087): The master clock for this clock assignment could not be derived. Clock: inst1|altpll_component|auto_generated|pll1|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: inst1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: inst1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock CLOCK_50 is never referenced in any input or output delay assignment.
Warning (332087): The master clock for this clock assignment could not be derived. Clock: inst1|altpll_component|auto_generated|pll1|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: inst1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: inst1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock CLOCK_50 is never referenced in any input or output delay assignment.
Warning (332087): The master clock for this clock assignment could not be derived. Clock: inst1|altpll_component|auto_generated|pll1|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: inst1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: inst1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock CLOCK_50 is never referenced in any input or output delay assignment.
Warning (332087): The master clock for this clock assignment could not be derived. Clock: inst1|altpll_component|auto_generated|pll1|clk[0] was not created.
Warning (332035): No clocks found on or feeding the specified source node: inst1|altpll_component|auto_generated|pll1|inclk[0]
Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: inst1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000
Warning (332061): Virtual clock CLOCK_50 is never referenced in any input or output delay assignment.
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发表于 2014-11-14 14:48:25
楼主
发表于 2014-11-19 13:14:33
