set_zero_interconnect_delay_mode 如何理解

W13675308408

ICC的data_setUp阶段这三句话是要干嘛啊
set_zero_interconnect_delay_mode true
redirect -tee zic.timing { report_timing }
set_zero_interconnect_delay_mode false
，下面是set_zero_interconnect_delay_mode 描述，谁来解释一下啊
This command enables or disables the zero interconnect delay mode.  The
       zero  interconnect  delay mode forces the timer to ignore contributions
       on a timing path from any wire capacitance in a design.  It forces  all
       wire  capacitance  to  be  as trivial as 0, regardless of the wire load
       model used in the design or any back-annotated capacitance on  a  wire.
       Disabling the mode allows the timer to consider the wire capacitance as
       it did before enabling the mode.


       The command is used primarily in preplacement and  postplacement  steps
       to assess design and constraint feasibility.  When the mode is enabled,
       the design is analyzed with only cell delay and the capacitance of  the
       pin load on all wires in the design to determine if the design can meet
       timing goals.  It also helps when debugging  potential  missing  timing
       exceptions  in  the constraints.  Zero interconnect delay mode must not
       be used in the final implementation step.

hsuyaochung542

這應該是一拿到netlist跟sdc後就要run
將net delay視為0(ideal)來看看timing有沒有meet constraint
如果在這個stage就看到很大的violation , 就要確認是那些violation , 可不可以waive或是false path等

check過後記得要設回false

jm2000

回复 2# hsuyaochung542


   跟楼上学习了，问问在什么情况下，我们可以设置线负载延时为0？