Zynq PL侧逻辑敏感列表中有主时钟以外的外部信号，结果implement后报错

lobster1989

Zynq7020, PL侧逻辑中在敏感列表加入主时钟以外的外部信号，结果implement后报错，各位有没有遇到如下情况，请问如何解决，谢谢！

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.

< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets AD0_SCLK_Fbk_IBUF] >

AD0_SCLK_Fbk_IBUF_inst (IBUF.O) is locked to IOB_X1Y15

and AD0_SCLK_Fbk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

mm201

请问一下您这个问题解决了吗？能否告知一下是怎么解决的？谢谢

greenpine

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets AD0_SCLK_Fbk_IBUF]