ZYNQ咨询：AXI总线条件下，PL处理器如何正常启动PS处理器中的DDR3控制器正常工作？

kaikai_2014

发帖咨询下：

    xc7z020(ZYNQ-7000)序列的SOC处理器中，PL处理器如何有效驱动PS处理中的ddr3控制器啊？


     我在PL处理器中利用状态机设计了一个Master，根据芯片架构，将PS处理器中的DDR3控制器视为SLAVE，Master与SLAVE直接通过

AXI4总线的HP端口实现互联（一对一，没有仲裁机制）。

    联合ILA、VIO调试时发现，PS处理器中的DDR3控制器(SLAVE)好像没有工作，因为当Master端的M_AXI_AWVALID始终被拉高时，

SLAVE端的应答信号S_AXI_AWREADY始终为低电平，Master端的状态机一直没有跳转，数据无法写入DDR3 SDRAM中。

我怀疑是PS处理器中的DDR3控制器没有工作，故发帖咨询下。（调用过Processing_system7的）

问题定位为： PS处理器中的DDR3控制器（SLAVE）没有工作，请问该如何解决？或者建议?

（另外：Master中的AMBA握手协议的状态机的确是工作了，但是状态无法正常跳转下去）

nj_yanglu

同问！怎么没有大虾回复。

kaikai_2014

同问！怎么没有大虾回复。
nj_yanglu 发表于 2014-10-29 22:11

                               
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   兄弟，已经搞定了，是SOC没跑起来的原因。

pingis58

楼主，我也正要做PL自己写AXI的IP核控制DDR。ZYNQ如何做功能仿真啊。还 只需要写IP核的时候，在ISE里做下功能仿真，在ZYNQ里直接调用，不需要仿真。

kaikai_2014

楼主，我也正要做PL自己写AXI的IP核控制DDR。ZYNQ如何做功能仿真啊。还 只需要写IP核的时候，在ISE里做下功 ...
pingis58 发表于 2014-11-12 11:03

                               
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        我没用modelsim仿出来，您可以尝试使用vivado自带的仿真器仿真下；

ZYNQ SOC平台包括软体平台和硬体平台，在VIVADO环境中进行硬体平台设计，在SDK中进行软体平台设计；DDR3控制器被内置在PS处理器中，是个硬编码IP核，只需要在设计PS处理器硬体时，配置适当的参数就行；

    PS处理器硬体配置完成后，DDR3控制器的接口以AXI4 SLAVE端口形式存在，只需要严格按照AXI4总线协议设计匹配的数字电路ddr3_master就可以驱动DDR3 SDRAM了；


实际应用中，可以严格按照AXI4总线协议规定的“握手”流程“利用状态机风格进行”串行“设计，即数据传输完成后再启动下一批次的数据传输，可靠性高，带宽利用率最低；也可以地址通道、数据通道、握手通道三级流水线进行设计，可靠性低，带宽利用率最高；

  带宽利用率与可靠性是一对矛盾；




`timescale 1ns / 10ps

module tb_master(
M_AXI_ACLK
,
M_AXI_RSTn
,
M_AXI_INTQ
,//From
VIO(Vitual Input/Output)

//WRITE
ADDRESS
CHANNEL
INTERFACE
M_AXI_AWID
,
M_AXI_AWADDR
,
M_AXI_AWLEN
,
M_AXI_AWSIZE
,
M_AXI_AWBURST
,
//
Burst
Type
M_AXI_AWLOCK
,
//
Lock Type,AXI4 is
not
supporting it...
M_AXI_AWCACHE
,
//
Memory Type
M_AXI_AWPROT
,
//
Protection Type
M_AXI_AWQOS
,
//
Quality
of Service
M_AXI_AWREGION
,
//
Region Identifier
M_AXI_AWUSER
,
//
User Signal
M_AXI_AWVALID
,
M_AXI_AWREADY
,

//WRITE
DATA CHANNEL INTERFACE
M_AXI_WID
,
M_AXI_WDATA
,
M_AXI_WSTRB
,
M_AXI_WLAST
,
M_AXI_WUSER
,
//user define
its
function selfly...
M_AXI_WVALID
,
M_AXI_WREADY
,

//WRITE
RESPONSE CHANNELS
INTERFACE:
M_AXI_BID
,
M_AXI_BRESP
,
M_AXI_BUSER
,
//user define
its
function selfly...
M_AXI_BVALID
,
M_AXI_BREADY
,

//READ ADDRESS CHANNELS
INTERFACE:
M_AXI_ARID
,
M_AXI_ARADDR
,
M_AXI_ARLEN
,
M_AXI_ARSIZE
,
M_AXI_ARBURST
,
M_AXI_ARLOCK
,
M_AXI_ARCACHE
,
M_AXI_ARPROT
,
M_AXI_ARQOS
,
M_AXI_ARREGION
,
M_AXI_ARUSER
,
M_AXI_ARVALID
,
M_AXI_ARREADY
,

//READ DATA
CHANNELS INTERFACE:
M_AXI_RID
,
M_AXI_RDATA
,
M_AXI_RRESP
,
M_AXI_RLAST
,
M_AXI_RUSER
,
//user define
its
function selfly...
M_AXI_RVALID
,
M_AXI_RREADY

//ddr3 interface to
drive
the
ddr3 controller
embed
in PS
Processor
//RAS_N
,
//3'b000-Load
Mode;
3'b001-Auto
Refresh;3'b010-Precharge;3'b011-Bank Active; 3'b100-write; 3'b101-Read;3'b111-NOP(IDLE)
//CAS_N
,
//WE

//
);

parameter

AW
=
32,

HLEN
=
32
;


parameter
[HLEN-1:0]
HLENGTH=32'd1024;


//enum
for
AXI_WRITE_ADDRESS
CHANNEL
WITH SYSTEM
VERILOG
FOR
DIGITAL
SYSTEM DESIGN
enum
logic
[11:0]
{AXI_AWIDLE
=
12'h1,

AXI_AWREADY
=
12'h2,

AXI_AWCTRL
=
12'h4,

AXI_AWVALID
=
12'h8,


AXI_WREADY
=
12'h10,

AXI_WCTRL
=
12'h20,


AXI_WVALID
=
12'h40,


AXI_WDATA
=
12'h80,


AXI_BVALID
=
12'h100,

AXI_BREADY
=
12'h200,


AXI_BRESP
=
12'h400,


AXI_BSTOP
=
12'h800}AWSTATE;


//enum
for
AXI_READ_ADDRESS
CHANNEL
WITH SYSTEM
VERILOG
FOR
DIGITAL
SYSTEM DESIGN
enum
logic
[11:0]
{
AXI_ARIDLE
=
12'h1,

AXI_ARREADY
=
12'h2,

AXI_ARCTRL
=
12'h4,

AXI_ARVALID
=
12'h8,



AXI_RCTRL
=
12'h20,

AXI_RVALID
=
12'h40,

AXI_RREADY
=
12'h80,

AXI_RDATA
=
12'h100,

AXI_RLAST
=
12'h200,

AXI_RRESP
=
12'h400,

AXI_RSTOP
=
12'h800}ARSTATE;


//Global Variables:
input
bit
M_AXI_ACLK
;
input
bit
M_AXI_RSTn
;
input
logic
[1:0]
M_AXI_INTQ
;
//
Present
the
write/read operation
2'b10-read 2'b01-write

//WRITE
ADDRESS
CHANNEL
INTERFACE
output
logic
[5
:0]
M_AXI_AWID
;
output
logic
[AW-1:0]
M_AXI_AWADDR
;
output
logic
[3
:0]
M_AXI_AWLEN
;
//
AWBURST="INC"
"FIXED"
output
logic
[2
:0]
M_AXI_AWSIZE
;

output
logic
[1:0]
M_AXI_AWBURST
;
output
logic
[1:0]
M_AXI_AWLOCK
;
output
logic
[3:0]
M_AXI_AWCACHE
;
output
logic
[2:0]
M_AXI_AWPROT
;
output
logic
[3:0]
M_AXI_AWQOS
;
output
logic
[3:0]
M_AXI_AWREGION
;
output
logic
[3:0]
M_AXI_AWUSER
;

output
logic
M_AXI_AWVALID
;
input
logic
M_AXI_AWREADY
;


//WRITE
DATA CHANNEL INTERFACE

output
logic
[5
:0]
M_AXI_WID
;
output
logic
[63
:0]
M_AXI_WDATA
;
output
logic
[7
:0]
M_AXI_WSTRB
;
output
logic
M_AXI_WLAST
;
output
logic
[3
:0]
M_AXI_WUSER
;
output
logic
M_AXI_WVALID
;
input
logic
M_AXI_WREADY
;

//WRITE
RESPONSE Channels
Interface:
input
logic
[5:0]
M_AXI_BID
;
input
logic
[1:0]
M_AXI_BRESP
;
input
logic
[3:0]
M_AXI_BUSER
;
input
logic
M_AXI_BVALID
;
output
logic
M_AXI_BREADY
;

//READ ADDRESS CHANNELS
INTERFACE:
output
logic
[5
:0]
M_AXI_ARID
;
output
logic
[AW-1:0]
M_AXI_ARADDR
;
output
logic
[3
:0]
M_AXI_ARLEN
;
output
logic
[2
:0]
M_AXI_ARSIZE
;
output
logic
[1:0]
M_AXI_ARBURST
;
output
logic
[1:0]
M_AXI_ARLOCK
;
output
logic
[3:0]
M_AXI_ARCACHE
;
output
logic
[2:0]
M_AXI_ARPROT
;
output
logic
[3:0]
M_AXI_ARQOS
;
output
logic
[3:0]
M_AXI_ARREGION
;
output
logic
[3
:0]
M_AXI_ARUSER
;
output
logic
M_AXI_ARVALID
;
input
logic
M_AXI_ARREADY
;


//READ DATA
CHANNELS INTERFACE:

input
logic
[5
:0]
M_AXI_RID
;
(*MARK_DEBUG="TRUE"*)input
logic
[63
:0]
M_AXI_RDATA
;
input
logic
[1:0]
M_AXI_RRESP
;
input
logic
M_AXI_RLAST
;
input
logic
[3:
0]
M_AXI_RUSER
;
(*MARK_DEBUG="TRUE"*)input
logic
M_AXI_RVALID
;
(*MARK_DEBUG="TRUE"*)output
logic
M_AXI_RREADY
;

//ddr3 interface
//output
logic
WEA
;
//output
logic
RAS_N
;
//output
logic
CAS_N
;



//Master Component Named tb_master (control
words
set)
assign

M_AXI_WSTRB
=
8'hff;

//M_AXI_RSTRB
=
{{BW{1'b1}}};

assign

M_AXI_AWID
=
6'd0,
//Master ID
Initialization,because of
only one master
for
patch
testing...

M_AXI_WID
=
6'd0,

M_AXI_ARID
=
6'd0;


assign

M_AXI_AWLEN
=
4'd15,

M_AXI_ARLEN
=
4'd15;//BurstLenth=8


assign

M_AXI_AWSIZE
=
3'b011,

M_AXI_ARSIZE
=
3'b011;

assign

M_AXI_AWBURST
=
2'b01,

M_AXI_ARBURST
=
2'b01;

assign

M_AXI_AWLOCK
=
2'd0,

M_AXI_ARLOCK
=
2'd0;


assign

M_AXI_AWCACHE
=4'd0,

M_AXI_ARCACHE
=4'd0;

assign

M_AXI_AWPROT
=
3'd0,

M_AXI_ARPROT
=
3'd0;


assign

M_AXI_AWQOS
=
4'd0,

M_AXI_ARQOS
=
4'd0;

assign

M_AXI_AWREGION
=
4'd0,

M_AXI_ARREGION
=
4'd0;

assign

M_AXI_AWUSER
=
4'd0,

M_AXI_WUSER
=
4'd0,

M_AXI_ARUSER
=
4'd0;

//M_AXI_BUSER
=
4'd0,

//M_AXI_RUSER
=
4'd0;




//M_AXI_ROM
instance
for
stimulus generating...the
sine data
will be
written
into ddr3
sdram
logic
[9:0]
M_AXI_ROM_ADDR;
(*MARK_DEBUG="TRUE"*)logic
[31:0]
cntt;

/*
logic
[1:0]
state0;
logic
[1:0]
M_AXI_INTQ_REG;
always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

M_AXI_INTQ_REG
<= 2'b00;
else

M_AXI_INTQ_REG
<= M_AXI_INTQ;


always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)begin

state0 <=
2'd0;

cntt <=
16'd0; end
else begin

case(state0)

2'b00:if({M_AXI_INTQ_REG,M_AXI_INTQ}==4'b0001)begin
state0 <=
2'b01; cntt
<= 16'd0;end

2'b01:
if(cntt==16'h7fff)begin
state0 <=
2'b10; cntt
<= 16'h0;end

else
begin
state0 <=
2'b01; cntt
<= cntt
+
1'b1;
end

2'b10:
begin
state0 <=
2'b00; cntt
<= 16'h0000; end

default:
begin
state0 <=
2'b00; cntt
<= 16'h0000; end

endcase

end
*/


always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

cntt <=
32'h0;
else

cntt <=
cntt + 32'd1;

/*
always_ff
@(posedge
M_AXI_ACLK)
if (M_AXI_WVALID &&
M_AXI_WREADY)
//if (M_AXI_WVALID &&
M_AXI_WREADY)

case
(M_AXI_ROM_ADDR[5:0])

6'b000000: M_AXI_WDATA <=
64'h0000000000000000;

6'b000001: M_AXI_WDATA <=
64'h0C8BD35E14DA1500;

6'b000010: M_AXI_WDATA <=
64'h18F8B83C69A60800;

6'b000011: M_AXI_WDATA <=
64'h25280C5DAB3E0800;

6'b000100: M_AXI_WDATA <=
64'h30FBC54D5D52C200;

6'b000101: M_AXI_WDATA <=
64'h3C56BA700DEC7200;

6'b000110: M_AXI_WDATA <=
64'h471CECE6B9A31C00;

6'b000111: M_AXI_WDATA <=
64'h5133CC9424775400;

6'b001000: M_AXI_WDATA <=
64'h5A827999FCEF2C00;//

6'b001001: M_AXI_WDATA <=
64'h62F201AC545CF800;

6'b001010: M_AXI_WDATA <=
64'h6A6D98A43A868400;

6'b001011: M_AXI_WDATA <=
64'h70E2CBC602F6B800;

6'b001100: M_AXI_WDATA <=
64'h7641AF3CCA351000;

6'b001101: M_AXI_WDATA <=
64'h7A7D055B18B76400;

6'b001110: M_AXI_WDATA <=
64'h7D8A5F3FDD72B800;

6'b001111: M_AXI_WDATA <=
64'h7F62368F44948C00;

6'b010000: M_AXI_WDATA <=
64'h7FFFFFFFFFFFF800;

6'b010001: M_AXI_WDATA <=
64'h7F62368F44949000;

6'b010010: M_AXI_WDATA <=
64'h7D8A5F3FDD72B800;

6'b010011: M_AXI_WDATA <=
64'h7A7D055B18B76400;

6'b010100: M_AXI_WDATA <=
64'h7641AF3CCA351000;

6'b010101: M_AXI_WDATA <=
64'h70E2CBC602F6BC00;

6'b010110: M_AXI_WDATA <=
64'h6A6D98A43A868800;

6'b010111: M_AXI_WDATA <=
64'h62F201AC545D0000;

6'b011000: M_AXI_WDATA <=
64'h5A827999FCEF3000;//

6'b011001: M_AXI_WDATA <=
64'h5133CC9424775400;

6'b011010: M_AXI_WDATA <=
64'h471CECE6B9A31C00;

6'b011011: M_AXI_WDATA <=
64'h3C56BA700DEC7A00;

6'b011100: M_AXI_WDATA <=
64'h30FBC54D5D52C600;

6'b011101: M_AXI_WDATA <=
64'h25280C5DAB3E0A00;

6'b011110: M_AXI_WDATA <=
64'h18F8B83C69A61500;

6'b011111: M_AXI_WDATA <=
64'h0C8BD35E14DA1D00;

6'b100000: M_AXI_WDATA <=
64'h000000000000046A;

6'b100001: M_AXI_WDATA <=
64'hF3742CA1EB25E800;

6'b100010: M_AXI_WDATA <=
64'hE70747C39659F000;

6'b100011: M_AXI_WDATA <=
64'hDAD7F3A254C20000;

6'b100100: M_AXI_WDATA <=
64'hCF043AB2A2AD4000;

6'b100101: M_AXI_WDATA <=
64'hC3A9458FF2139000;

6'b100110: M_AXI_WDATA <=
64'hB8E31319465CF000;

6'b100111: M_AXI_WDATA <=
64'hAECC336BDB88B000;

6'b101000: M_AXI_WDATA <=
64'hA57D86660310D000;

6'b101001: M_AXI_WDATA <=
64'h9D0DFE53ABA31000;

6'b101010: M_AXI_WDATA <=
64'h9592675BC5798000;

6'b101011: M_AXI_WDATA <=
64'h8F1D3439FD094800;

6'b101100: M_AXI_WDATA <=
64'h89BE50C335CAF800;

6'b101101: M_AXI_WDATA <=
64'h8582FAA4E748A000;

6'b101110: M_AXI_WDATA <=
64'h8275A0C0228D5000;

6'b101111: M_AXI_WDATA <=
64'h809DC970BB6B7000;

6'b110000: M_AXI_WDATA <=
64'h8000000000000800;

6'b110001: M_AXI_WDATA <=
64'h809DC970BB6B7000;

6'b110010: M_AXI_WDATA <=
64'h8275A0C0228D4800;

6'b110011: M_AXI_WDATA <=
64'h8582FAA4E748A000;

6'b110100: M_AXI_WDATA <=
64'h89BE50C335CAF000;

6'b110101: M_AXI_WDATA <=
64'h8F1D3439FD094000;

6'b110110: M_AXI_WDATA <=
64'h9592675BC5797000;

6'b110111: M_AXI_WDATA <=
64'h9D0DFE53ABA30800;

6'b111000: M_AXI_WDATA <=
64'hA57D86660310D000;

6'b111001: M_AXI_WDATA <=
64'hAECC336BDB88A000;

6'b111010: M_AXI_WDATA <=
64'hB8E31319465CE000;

6'b111011: M_AXI_WDATA <=
64'hC3A9458FF2138000;

6'b111100: M_AXI_WDATA <=
64'hCF043AB2A2AD2800;

6'b111101: M_AXI_WDATA <=
64'hDAD7F3A254C1F000;

6'b111110: M_AXI_WDATA <=
64'hE70747C39659E800;

6'b111111: M_AXI_WDATA <=
64'hF3742CA1EB25F000;

endcase
*/

(* rom_style="block" *)
logic
[63:0] M_AXI_ROM [1023:0];

initial

$readmemh("../matlab/sint.dat",
M_AXI_ROM, 0,
1023);

always @(posedge M_AXI_ACLK)
if(M_AXI_WVALID
&&
M_AXI_WREADY)

M_AXI_WDATA <=
M_AXI_ROM[M_AXI_ROM_ADDR];

always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

M_AXI_ROM_ADDR <=
10'd0;
else if(AWSTATE==AXI_AWIDLE)
        M_AXI_ROM_ADDR <=
10'd0;
else if(M_AXI_WVALID &&
M_AXI_WREADY)

M_AXI_ROM_ADDR <=
M_AXI_ROM_ADDR
+
1'b1;
else

M_AXI_ROM_ADDR <=
M_AXI_ROM_ADDR;

//..................WRITE-ADDRESS/WRITE-DATA_GENERATING
WITH
STATE-MACHINE
CIRCUITS.................M_AXI_AWREADY'S PHASE IS
AHEAD
OF M_AXI_AWVALID
M_AXI_WREADY IS
BEFORE M_AXI_WVALID
HANDSHAKING

logic
[31:0]
cnt0;
(*MARK_DEBUG="TRUE"*)logic
[3 :0]
cnt16a;

always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)begin

cnt16a
<= 4'd0;

cnt0 <=
32'd0;

AWSTATE
<=
AXI_AWIDLE;
end
else begin

case(AWSTATE)

AXI_AWIDLE
:if(cntt[12:0]==13'd1)
begin
AWSTATE
<= AXI_AWREADY;
cnt0 <=
32'd0;cnt16a
<= 4'd0;end




AXI_AWREADY
:
if(M_AXI_AWREADY)
AWSTATE
<= AXI_AWCTRL;




AXI_AWCTRL
:
AWSTATE
<= AXI_AWVALID;
//inserting a state



AXI_AWVALID
:
AWSTATE
<= AXI_WREADY;



//Inserting
State-Machine
to process the 8 data
through
DDR3 SDRAM


AXI_WREADY
:
if(M_AXI_WREADY)
AWSTATE
<=
AXI_WCTRL;



AXI_WCTRL
:
AWSTATE
<= AXI_WVALID;//Handshaking
is successfully,so the next
setp is
transmitting the data



AXI_WVALID
:
if(M_AXI_WREADY) AWSTATE <=
AXI_WDATA;



AXI_WDATA
:if(M_AXI_WREADY)begin

if(cnt16a==4'd15)
begin cnt16a
<=
4'd0;
AWSTATE
<=
AXI_BVALID;
end

else
begin
cnt16a
<= cnt16a
+
4'd1;
AWSTATE
<=
AXI_WDATA; end

end




AXI_BVALID
:
if(AXI_BVALID) AWSTATE
<= AXI_BREADY;



AXI_BREADY
:
AWSTATE<=
AXI_BRESP;



AXI_BRESP
:
if (M_AXI_BRESP==2'b00)AWSTATE
<= AXI_BSTOP;



AXI_BSTOP
:
if(cnt0==HLENGTH)
begin
AWSTATE
<= AXI_AWIDLE; cnt0
<= 32'd0;
end

else
begin
AWSTATE
<= AXI_AWREADY;
cnt0 <=
cnt0 + 32'd16;end



default
:
AWSTATE
<= AXI_AWIDLE;

endcase

end


always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

M_AXI_AWVALID
<=
1'b0;
else if(AWSTATE==AXI_AWCTRL)

M_AXI_AWVALID
<= 1'b1;
else

M_AXI_AWVALID
<= 1'b0;


always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

M_AXI_WVALID <=
1'b0;
else if(AWSTATE==AXI_WDATA )

M_AXI_WVALID <=
1'b1;
else

M_AXI_WVALID <=
1'b0;

always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

M_AXI_BREADY <=
1'b0;
else if(|cnt16a)

M_AXI_BREADY <=1'b1;
else

M_AXI_BREADY <=
1'b0;



always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

M_AXI_AWADDR
<=32'h0;
else if(AWSTATE==AXI_AWIDLE)

M_AXI_AWADDR
<= 32'h1D00_0000;//From
Huang.QiBo@avnet.com
else if(AWSTATE==AXI_AWCTRL)

M_AXI_AWADDR <=
M_AXI_AWADDR + 32'd128;

//--------------------------------WRITE_ADDRESS
DESCRIPTION
IS END---------------------------------------

always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

M_AXI_WLAST
<= 1'b0;
else if(cnt16a==4'd15)

M_AXI_WLAST
<=1'b1;
else

M_AXI_WLAST
<= 1'b0;

//WRITE
CHANNEL
AND
WRITE_ADDRESS
CHANNEL
DESCRIPTION
IS SUCCESSFULLY...








//**********************************************************************
//
//
//
//
//
kingsine.corp.
//

//
//
//
//**************************************************************************












//--------------------------------------------------------------------------------------------
//DMA
is better

//READ-CHANNELs
STATE
MACHINE
CONTROL
the
Circuit's
Behavior,expecially
handshakin circuit

(*MARK_DEBUG="TRUE"*)logic
[31:0]
cnt1;
always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)begin

cnt1 <=
32'd0;

ARSTATE
<= AXI_ARIDLE; end
else begin

case(ARSTATE)

AXI_ARIDLE
:
if(cntt[12:0]==13'd4095)
begin
ARSTATE
<= AXI_ARREADY;
cnt1 <=
32'd0;end




AXI_ARREADY
:
if(M_AXI_ARREADY)
ARSTATE
<= AXI_ARCTRL;




AXI_ARCTRL
:
ARSTATE
<= AXI_ARVALID;
//AXI_ARVALID
IS GENERATING



AXI_ARVALID
: if(M_AXI_RVALID)
ARSTATE
<= AXI_RVALID;



AXI_RVALID
:
ARSTATE
<= AXI_RDATA;
//AXI_RREADY IS
GENERATING



AXI_RDATA
:
if(M_AXI_RVALID) begin

if(M_AXI_RLAST ==
1'b1)
ARSTATE
<= AXI_RLAST;

else ARSTATE <=
AXI_RDATA; end



AXI_RLAST
:
if(M_AXI_RRESP==2'b00)ARSTATE
<= AXI_RRESP;




AXI_RRESP
:
if(cnt1==HLENGTH)
begin
ARSTATE
<= AXI_ARIDLE; cnt1
<= 32'd0;end

else begin ARSTATE <=
AXI_ARREADY;
cnt1 <=
cnt1 + 32'd16;
end

default
:
ARSTATE
<= AXI_ARIDLE;

endcase

end

always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

M_AXI_ARVALID
<=
1'b0;
else if(ARSTATE==AXI_ARCTRL)
//else if(ARSTATE==AXI_ARCTRL
|| ARSTATE==AXI_ARVALID)

M_AXI_ARVALID
<= 1'b1;
else //if(ARSTATE==AXI_ARIDLE)//else

M_AXI_ARVALID
<= 1'b0;

always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

M_AXI_ARADDR
<=32'h0;
else if(ARSTATE==AXI_ARIDLE)

M_AXI_ARADDR
<= 32'h1D00_0000;//From
Huang.QiBo@avnet.com
else if(ARSTATE==AXI_ARCTRL)

M_AXI_ARADDR <=
M_AXI_ARADDR + 32'd128;

always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

M_AXI_RREADY
<= 1'b0;
else if(ARSTATE==AXI_RDATA)

M_AXI_RREADY <=
1'b1;
else

M_AXI_RREADY <=
1'b0;


// Not supported and hence assigned
zeros



//Testing
Logic automatic operation
(*MARK_DEBUG="TRUE"*)
logic
[1:0]
ERR_REG;
(*MARK_DEBUG="TRUE"*)
logic
[63:0]
T_AXI_RDATA;

logic
[9:0]
T_AXI_ROM_ADDR;
(* rom_style="block" *)
logic
[63:0] T_AXI_ROM [1023:0];

initial

$readmemh("../matlab/sint.dat",
T_AXI_ROM, 0,
1023);

always @(posedge M_AXI_ACLK)
if(M_AXI_RVALID
&&
M_AXI_RREADY)

T_AXI_RDATA <=
T_AXI_ROM[T_AXI_ROM_ADDR];

always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

T_AXI_ROM_ADDR <=
10'd0;
else if(ARSTATE==AXI_ARIDLE)

T_AXI_ROM_ADDR <=
10'd0;
else if(M_AXI_RVALID &&
M_AXI_RREADY)

T_AXI_ROM_ADDR <=
T_AXI_ROM_ADDR
+
1'b1;
else

T_AXI_ROM_ADDR <=
T_AXI_ROM_ADDR;

/*
always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

M_AXI_RDATA_REG
<=
64'h0;
else

M_AXI_RDATA_REG
<=
M_AXI_RDATA;
*/

always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

ERR_REG
<= 2'd0;
else
if(M_AXI_RVALID && M_AXI_RREADY) begin
            if(M_AXI_RDATA==T_AXI_RDATA)

      ERR_REG <=
2'b11;

        else

ERR_REG
<= 2'b00;   end



(*MARK_DEBUG="TRUE"*)logic
[12:0]
wtt_reg;
(*MARK_DEBUG="TRUE"*)logic
[12:0]
rtt_reg;
(*MARK_DEBUG="TRUE"*)logic
wr_en;
(*MARK_DEBUG="TRUE"*)logic
rd_en;
always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

wr_en <=
1'b0;
else if(cnt0==HLENGTH)

wr_en <=
1'b1;
else

wr_en
<= 1'b0;

always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

rd_en
<= 1'b0;
else if(cnt1==HLENGTH)

rd_en
<= 1'b1;
else

rd_en
<= 1'b0;





always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

wtt_reg
<= 13'h0;
else if(wr_en)

wtt_reg
<= cntt[12:0];
else

wtt_reg
<= wtt_reg;

always_ff
@(posedge
M_AXI_ACLK or
negedge
M_AXI_RSTn)
if(~M_AXI_RSTn)

rtt_reg
<= 13'h0;
else if(rd_en)

rtt_reg
<= cntt[12:0]-13'd4095;
else

rtt_reg
<= rtt_reg;


endmodule







利用逻辑分析仪进行全自动化设计检错的简单ddr3_master设计（自己修改下单音信号源、伪随机信号源）

zyj3334683

回复 1# kaikai_2014

楼主，你贴出来的代码能不能发我一份研读一下？我复制下来排版问题看起来近视高了好多度...最近也考虑用axi总线做个sdram接口，自己的几个模块做master控制，将axi interconnecte做仲裁器用，mig生成axi slave的sdram接口。
要是方便的话，能不能发我邮箱研习一下？448274685@qq.com。先谢过~

shiweishiwei

学些顶贴！！！！！！！！！

ta1ent

请问最后成功了吗？能不能具体分享下设计过程？？

chuanchuan304

回复 3# kaikai_2014


   您好，我现在遇到相同的问题了，AWVALID为高后，一直等不到AREADY信号；我的PS端只跑了helloworld,怎样检查PS端的DDR核有没有跑起来呢？

nofoolish

回复 3# kaikai_2014


  大侠。。。能否指导一下，同样遇到问题