超帧基本帧

1074048921

mtx_synch仿真得到的结果：
   basic_frame_last2_word_ind_i表示当tx中word_cnt(5 downto 0) = "111101"也就是一个基本帧的倒数第二个字。否则为0；
   basic_frame_last_word_ind_i为basic_frame_last2_word_ind_i打一拍后，也就是一个基本帧的倒数第一个字。
   basic_frame_last_word_ind<=basic_frame_last_word_ind_i,
   basic_frame_cnt_pre1在basic_frame_last2_word_ind_i为1时增加1表示基本帧的数目增加1，此时刚好最后一个字加上基本帧。
   basic_frame_cnt为basic_frame_cnt_pre1打一拍之后的值，也是在一个基本帧完全形成以后能加1，真正的代表基本帧的数目。
   basic_frame_nr_pre1和basic_frame_cnt_pre1相等，而basic_frame_nr和basic_frame_cnt相等。
   iq_tx_pulse_cpri_first在word_number等于111111时变高。在mtx_synch中作为输出，给tx_iq中的iq_tx_pulse_cpri，经过一拍，也就是
一个基本帧真正的形成后，使buff_out_addr变成“00000000”；
   hfn_cnt和hfn_tx_nr是一样的，且都是在其他的条件满足时，在word_number变0时一起变1，而pulse_10ms_tx在新的一个无线帧来时，
表高，即hfn_cnt变0是同步的。pulse_10ms_tx告诉frame_delay_measure一个新的无线帧已经开始。
   iq_tx_pulse_cpri_second无意义。
   word_number对基本帧的计数。

tx_mux:
  tx_hdlc_rate和hdlc_reg_data没有意义。
  basic_frame_first_word是basic_frame_last_word_ind打一拍的真正的代表基本帧的开头。

ethernet_tx模块：
ethernet_tx根据ethernet_tx_pulse和tx_st给tx_data_eth赋值。按照mac的结构
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-----------------------------------------------------------
entity mrx_synch_tb is
end entity mrx_synch_tb;
-----------------------------------------------------------
architecture testbench of mrx_synch_tb is

  component mrx_synch is
    port (

      speed_sel              : in  std_logic_vector(1 downto 0);
    reset                  : in  std_logic;
    sync_in                : in  std_logic;

    -- To/From the MGT
    rx_clk                 : in  std_logic;
    rx_data                : in  std_logic_vector(15 downto 0);
    rx_iscomma             : in  std_logic_vector(1 downto 0);
    -- Status to the outside

frame_10ms_start
: out std_logic;
    hfn_rx_nr              : out std_logic_vector(7 downto 0);
    loss_of_frame          : out std_logic;
    loss_of_signal         : out std_logic;

SERDES_REALIGN
: out std_logic;
    -- To the receive side downstream us
    basic_frame_first_word : out std_logic;
    basic_frame_last_word
: out std_logic;
    basic_frame_number     : out std_logic_vector(5 downto 0);

word_number
: out std_logic_vector(5 downto 0);

sync_token
: out std_logic_vector(7 downto 0);

sync_state
: out std_logic_vector(3 downto 0);

pre_sync_state
: out std_logic_vector(3 downto 0);

hdlc_reg_data
: out std_logic_vector(15 downto 0);

ethernet_rx_pulse
: out std_logic;

-- rru phy word

phy_reset_indicate
: out std_logic_vector(7 downto 0);


rru_id_1
: out std_logic_vector(7 downto 0);

rru_id_2
: out std_logic_vector(7 downto 0);

rru_id_3
: out std_logic_vector(7 downto 0);

rru_id_4
: out std_logic_vector(7 downto 0);

rru_id_5
: out std_logic_vector(7 downto 0);

rru_id_6
: out std_logic_vector(7 downto 0);

rru_id_7
: out std_logic_vector(7 downto 0);

rru_id_8
: out std_logic_vector(7 downto 0);

rru_id_9
: out std_logic_vector(7 downto 0);

rru_id_10
: out std_logic_vector(7 downto 0);

rru_id_11
: out std_logic_vector(7 downto 0);

rru_id_12
: out std_logic_vector(7 downto 0);

downlink_indicate_rx
: out std_logic_vector(15 downto 0)

);

end component;


-- Clock period definitions
    constant rx_clk_period : time := 10 ns;




    signal  speed_sel                   :  std_logic_vector(1 downto 0):="01";
   
signal  reset                       :   std_logic:='0';
   
signal  sync_in                     :   std_logic:='1';

    -- To/From the MGT
   
signal  rx_clk                      :   std_logic:='0';
   
signal  rx_data                     :   std_logic_vector(15 downto 0):=x"0000";
   
signal  rx_iscomma                  :   std_logic_vector(1 downto 0):="10";
    -- Status to the outside

signal  frame_10ms_start
        :  std_logic;
   
    signal  hfn_rx_nr                   :  std_logic_vector(7 downto 0);
   
signal  loss_of_frame               :  std_logic;
   
signal  loss_of_signal              :  std_logic;

signal  SERDES_REALIGN
    :  std_logic;
    -- To the receive side downstream us
   
signal  basic_frame_first_word      :  std_logic;
   
    signal  basic_frame_last_word   
:  std_logic;
   
    signal  basic_frame_number          :  std_logic_vector(5 downto 0);

signal  word_number
    :  std_logic_vector(5 downto 0);

signal  sync_token
:  std_logic_vector(7 downto 0);

signal  sync_state
:  std_logic_vector(3 downto 0);

signal  pre_sync_state
    :  std_logic_vector(3 downto 0);

signal  hdlc_reg_data
:  std_logic_vector(15 downto 0);

signal  ethernet_rx_pulse
   
:  std_logic;

-- rru phy word

signal  phy_reset_indicate
    :  std_logic_vector(7 downto 0);


signal  rru_id_1
:  std_logic_vector(7 downto 0);


signal  rru_id_2
:  std_logic_vector(7 downto 0);

signal  rru_id_3
:  std_logic_vector(7 downto 0);

signal  rru_id_4
:  std_logic_vector(7 downto 0);


signal  rru_id_5
:  std_logic_vector(7 downto 0);

signal  rru_id_6
:  std_logic_vector(7 downto 0);

signal  rru_id_7
:  std_logic_vector(7 downto 0);

signal  rru_id_8
:  std_logic_vector(7 downto 0);


signal  rru_id_9
:  std_logic_vector(7 downto 0);

signal  rru_id_10
:  std_logic_vector(7 downto 0);

signal  rru_id_11
:  std_logic_vector(7 downto 0);

signal  rru_id_12
:  std_logic_vector(7 downto 0);

signal  downlink_indicate_rx
    :  std_logic_vector(15 downto 0);









begin

uut : mrx_synch

  port map (

    speed_sel              =>
speed_sel,

    reset                  =>
reset,

sync_in                => sync_in,--: in  std_logic;


    -- To/From the MGT

    rx_clk                 =>
rx_clk,

    rx_data                =>
rx_data,

    rx_iscomma             =>
rx_iscomma,

    -- Status to the outside

frame_10ms_start
=> frame_10ms_start,

    hfn_rx_nr              =>
hfn_rx_nr,

    loss_of_frame          =>
loss_of_frame,

    loss_of_signal         =>
open,

SERDES_REALIGN
=> SERDES_REALIGN,--: out std_logic;

    -- To the receive side downstream us

    basic_frame_first_word =>
basic_frame_first_word,

    basic_frame_last_word
=>
basic_frame_last_word,

    basic_frame_number     =>
basic_frame_number,

word_number
=> word_number,

sync_token
=> sync_token,

sync_state
=> sync_state,

pre_sync_state
=> pre_sync_state,

hdlc_reg_data
=> hdlc_reg_data,

ethernet_rx_pulse
=> ethernet_rx_pulse,--: out std_logic;

-- rru phy word

phy_reset_indicate
=> phy_reset_indicate,--: out std_logic_vector(7 downto 0);


rru_id_1
=>
rru_id_1,--: out std_logic_vector(7 downto 0);

rru_id_2
=>
rru_id_2,--: out std_logic_vector(7 downto 0);

rru_id_3
=>
rru_id_3,--: out std_logic_vector(7 downto 0);

rru_id_4
=> rru_id_4,--: out std_logic_vector(7 downto 0);

rru_id_5
=> rru_id_5,--: out std_logic_vector(7 downto 0);

rru_id_6
=> rru_id_6,--: out std_logic_vector(7 downto 0);

rru_id_7
=> rru_id_7,--: out std_logic_vector(7 downto 0);

rru_id_8
=> rru_id_8,--: out std_logic_vector(7 downto 0);

rru_id_9
=> rru_id_9,--: out std_logic_vector(7 downto 0);

rru_id_10
=> rru_id_10,--: out std_logic_vector(7 downto 0);

rru_id_11
=> rru_id_11,--: out std_logic_vector(7 downto 0);

rru_id_12
=> rru_id_12,--: out std_logic_vector(7 downto 0)

downlink_indicate_rx
=> downlink_indicate_rx--: out std_logic_vector(15 downto 0)

);



-- Clock process definitions
        rx_clk_process :process
        begin

    rx_clk <= '0';

    wait for rx_clk_period/2;

    rx_clk <= '1';

    wait for rx_clk_period/2;
        end process;



    tb :process

    begin

    reset <='1';

wait for 20ns;

reset <='0';

rx_iscomma <= "00";

rx_data <= x"aaaa";

wait for 10ns;

rx_data <= x"bbbb";


wait for 10ns;

rx_data <= x"cccc";

        wait for 10ns;


rx_data <= x"dddd";

        wait for 10ns;


rx_data <= x"eeee";

wait for 10ns;

rx_data <= x"ffff";


wait for 10ns;

rx_data <= x"1111";

        wait for 10ns;


rx_data <= x"2222";


wait for 10ns;


rx_data <= x"3333";

wait for 10ns;

rx_data <= x"4444";


wait for 10ns;

rx_data <= x"5555";

        wait for 10ns;


rx_data <= x"6666";


wait for 10ns;


rx_data <= x"7777";

wait for 10ns;

rx_data <= x"8888";


wait for 10ns;

rx_data <= x"9999";

        wait for 10ns;


rx_data <= x"a1a1";
        wait for 10ns;


rx_data <= x"b1b1";

wait for 10ns;

rx_data <= x"c1c1";


wait for 10ns;

rx_data <= x"d1d1";

        wait for 10ns;


rx_data <= x"e1e1";


wait for 10ns;


rx_data <= x"f1f1";

wait for 10ns;

rx_data <= x"a2a2";


wait for 10ns;

rx_data <= x"b2b2";

        wait for 10ns;


rx_data <= x"c2c2";


wait for 10ns;


rx_data <= x"d2d2";

wait for 10ns;

rx_data <= x"e2e2";


wait for 10ns;

rx_data <= x"f2f2";

        wait for 10ns;


rx_data <= x"a3a3";


wait for 10ns;


rx_data <= x"b3b3";

wait for 10ns;

rx_data <= x"d3d3";


wait for 10ns;

rx_data <= x"e3e3";

        wait for 10ns;


rx_data <= x"f3f3";


wait for 10ns;
        rx_data <= x"a4a4";

wait for 10ns;

rx_data <= x"b4b4";


wait for 10ns;

rx_data <= x"c4c4";

        wait for 10ns;


rx_data <= x"d4d4";

        wait for 10ns;


rx_data <= x"e4e4";

wait for 10ns;

rx_data <= x"f4f4";


wait for 10ns;

rx_data <= x"a5a5";

        wait for 10ns;


rx_data <= x"b5b5";


wait for 10ns;


rx_data <= x"c5c5";

wait for 10ns;

        rx_data <= x"d5d5";

wait for 10ns;

rx_data <= x"e5e5";


wait for 10ns;

rx_data <= x"f5f5";

        wait for 10ns;


rx_data <= x"a6a6";
        wait for 10ns;


rx_data <= x"b6b6";

wait for 10ns;

rx_data <= x"c6c6";


wait for 10ns;

rx_data <= x"d6d6";

        wait for 10ns;


rx_data <= x"e6e6";


wait for 10ns;


rx_data <= x"f6f6";

wait for 10ns;


rx_data <= x"a7a7";
        wait for 10ns;


rx_data <= x"b7b7";

wait for 10ns;

rx_data <= x"c7c7";


wait for 10ns;

rx_data <= x"d7d7";

        wait for 10ns;


rx_data <= x"e7e7";


wait for 10ns;


rx_data <= x"f7f7";

wait for 10ns;


rx_data <= x"a8a8";
        wait for 10ns;


rx_data <= x"b8b8";

wait for 10ns;

rx_data <= x"c8c8";


wait for 10ns;

rx_data <= x"d8d8";

        wait for 10ns;


rx_data <= x"e8e8";


wait for 10ns;


rx_data <= x"f8f8";

wait for 10ns;


    end process;

end testbench;



--------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;--------------------------------------------------------------entity mtx_synch_tb is end entity mtx_synch_tb;--------------------------------------------------------------architecture test_bench of mtx_synch_tb is       -- Component Declaration for the Unit Under Test (UUT)      component mtx_synch     port(         reset          : in  std_logic;             speed_sel      : in  std_logic_vector(1 downto 0);         pll_ref_clk    : in  std_logic;         pulse_10ms            : in  std_logic;             pulse_10ms_tx         : out std_logic;             basic_frame_last_word_ind : out std_logic;             iq_tx_pulse_cpri_first        : out std_logic;             iq_tx_pulse_cpri_second        : out std_logic;             ethernet_tx_pulse        : out std_logic;         hfn_tx_nr      : out std_logic_vector(7 downto 0);             word_number         :        out std_logic_vector(5 downto 0);         basic_frame_nr : out std_logic_vector(5 downto 0);         basic_frame_nr_pre1 : out std_logic_vector(5 downto 0)         );    end component;      -- Clock period definitions    constant pll_ref_clk_period : time := 10 ns;                -- input        signal reset          :   std_logic :='0';        signal speed_sel      :   std_logic_vector(1 downto 0) :="01";        signal pll_ref_clk    :   std_logic :='0';    signal pulse_10ms     :   std_logic :='0';                -- output        signal pulse_10ms_tx                    :  std_logic;        signal basic_frame_last_word_ind    :  std_logic;        signal iq_tx_pulse_cpri_first            :  std_logic;        signal iq_tx_pulse_cpri_second            :  std_logic;        signal ethernet_tx_pulse                :  std_logic;    signal hfn_tx_nr                    :  std_logic_vector(7 downto 0);        signal word_number                        :  std_logic_vector(5 downto 0);    signal basic_frame_nr               :  std_logic_vector(5 downto 0);    signal basic_frame_nr_pre1          :  std_logic_vector(5 downto 0);      begin             uut : mtx_synch port map (                      reset => reset,              speed_sel => speed_sel,              pll_ref_clk => pll_ref_clk,              pulse_10ms => pulse_10ms,              pulse_10ms_tx => pulse_10ms_tx,              basic_frame_last_word_ind => basic_frame_last_word_ind,              iq_tx_pulse_cpri_first => iq_tx_pulse_cpri_first,              iq_tx_pulse_cpri_second => iq_tx_pulse_cpri_second,              ethernet_tx_pulse => ethernet_tx_pulse,              hfn_tx_nr => hfn_tx_nr,              word_number => word_number,              basic_frame_nr => basic_frame_nr,              basic_frame_nr_pre1=> basic_frame_nr_pre1                      );                                          -- Clock process definitions        pll_ref_clk_process :process        begin                    pll_ref_clk <= '0';                    wait for pll_ref_clk_period/2;                    pll_ref_clk <= '1';                    wait for pll_ref_clk_period/2;        end process;            tb :process        begin            reset <='1';                wait for 20ns;                reset <='0';                wait for 60ns;                pulse_10ms <= '1';                wait for 20ns;                pulse_10ms <= '0';        wait for 30ms;                        end process;                    end test_bench;
LIBRARY ieee;USE ieee.std_logic_1164.all;entity pulse_expander_tb isend entity;architecture test_bench of pulse_expander_tb is  COMPONENT pulse_expander IS        --元件声明    PORT(clk                        : in std_logic;                pulse_in        : in std_logic;                pulse_out        : out std_logic);  END COMPONENT;  signal clk:std_logic;  signal pulse_in,pulse_out:std_logic;  constant clk_period=10 ns;  BEGIN  DUT:pulse_expander PORT MAP( clk => clk, pulse_in => pulse_in, pulse_out => pulse_out);clk_gen:processbegin  clk <= '1';  wait for clk_period/2;  clk <= '0';  wait for clk_period/2;end process;tb:processbegin  wait for 10ns;  pulse_in <= '1';  wait for 80ns;  pulse_in <= '0';  wait for 1000ns;end process; end test_bench;