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各位大侠，小弟在做LVS的时候遇到了一个很奇怪的问题。网表里面的一个D触发器，foundry给的标准单元里的core cell 网表是没有二极管的，但是这个触发器的GDS文件显示有两个寄生的二极管，这样在做LVS的时候就说我的source网表里缺少二极管，请问这个问题怎么解决。还是我哪里弄错了，下面是LVS的report
Error: Different numbers of instances (see below).
layout CELL NAME: QDFFRBN
SOURCE CELL NAME: QDFFRBN
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 6 6
Nets: 17 17
Instances: 14 14 MN (4 pins)
14 14 MP (4 pins)
2 0 * D (2 pins)
------ ------
Total Inst: 30 28
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 6 6
Nets: 15 15
Instances: 4 4 MN (4 pins)
4 4 MP (4 pins)
2 0 * D (2 pins)
6 6 INV (2 pins)
2 2 NAND2 (3 pins)
------ ------
Total Inst: 18 16
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 D0(0.880,1.980) D(DION_EE2_UCFNLL) ** missing instance **
pos: GND:G ** GND **
neg: D:ID ** D **
--------------------------------------------------------------------------------------------------------------
2 D1(1.190,1.100) D(DION_EE2_UCFNLL) ** missing instance **
pos: GND:G ** GND **
neg: CK:ID ** CK **
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 6 6 0 0
Nets: 15 15 0 0
Instances: 4 4 0 0 MN(N_18_EE2_UCFNLL)
4 4 0 0 MP(P_18_EE2_UCFNLL)
0 0 2 0 D(DION_EE2_UCFNLL)
6 6 0 0 INV
2 2 0 0 NAND2
------- ------- --------- ---------
Total Inst: 16 16 2 0
o Layout Names That Are Missing In The Source:
Ports: VCC GND:G D:ID CK:ID RB:I Q:O
Nets: VCC GND:G D:ID CK:ID RB:I Q:O |
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创芯大讲堂
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发表于 2014-8-22 16:15:39
楼主
发表于 2014-8-24 15:24:51
