仿真时为什么pwm1和pwm3没有输出呢，请前辈们指教啊！！！

ll1057126122

第一段程序LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY pwmgen IS

generic

(   

f_len:natural:=9;  

delay_len:natural:=9;

dead:natural:=5

);



port(

rst,clk:in std_logic;

feedin:in std_logic;
        di:in std_logic;

--delay:in std_logic_vector(f_len-1 downto 0);

pwm1,pwm3,pwm2,pwm4ut std_logic

);
end entity pwmgen ;

architecture bhv of pwmgen is

signal tm,pwm10,pwm20,pwm30,pwm40:std_logic;

signal delay_r:std_logic_vector(delay_len+f_len-1 downto 0);

signal cmp,cmp_dead:std_logic_vector(f_len-1 downto 0);

signal f,fi:std_logic_vector(f_len-1 downto 0);

signal delay:std_logic_vector(f_len-1 downto 0):="011001100";

signal feedcount:std_logic_vector(11 downto 0):="000000000000";
signal close:std_logic:='0';
signal dis: std_logic;

component fcounter

generic

(   

f_len:natural:=9;  


f_delta:natural:=10

);

port(

rst,clk,di:in std_logic;

f,fiut std_logic_vector(f_len-1 downto 0);

tmut std_logic

);

end component;


begin
d1:process(clk,close)
    begin

if close='0' then

if clk'event and clk='1' then

   

    if feedcount<"111111111100" then
        feedcount<=feedcount+'1';
        dis<=di;
--        di1<=dis;

  else
          close<='1';

  dis<=feedin;
--
  di1<=dis;
        end if;

end if;

        else

  dis<=feedin;
--
  di1<=dis;
end if;
  
end process;

fc1:fcounter generic map(9,10) port map(rst,clk,dis,f,fi,tm);

delay_r<=delay*f;

cmp<=delay_r(delay_len+f_len-1 downto delay_len);

cmp_dead<="0"&f(f'length-1 downto 1)-dead;

--adad


d:process(clk,rst)

begin


if rst='0' then

pwm10<='0';

pwm20<='0';

pwm30<='0';

pwm40<='0';


elsif clk'event and clk='1' then

if (fi>=0 and fi<cmp ) then

if tm='1' then pwm10<='1';end if;

if tm='0' then pwm20<='1';end if;

else

pwm10<='0';

pwm20<='0';

end if;



if (fi>dead and fi<cmp_dead) then

if tm='1' then pwm30<='1';end if;

if tm='0' then pwm40<='1';end if;

else

pwm30<='0';

pwm40<='0';

end if;

end if;

end process;



pwm1<=pwm10 and pwm30;

pwm3<=pwm20 and pwm40;
   pwm2<=not dis;
   pwm4<=dis;

end bhv;

ll1057126122

第二段程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fcounter is
        generic
        (   
                f_len:natural:=9;  --棰戠巼鏈

ll1057126122

第二段程序LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fcounter is

generic

(   

f_len:natural:=9;  --棰戠巼鏈