求助：分频程序上板子时钟不稳定

qiudanyi1

module fp
(
    CLK_in,

RSTn,

CLK_out
);
input CLK_in;
input RSTn;
output CLK_out;
reg    CLK_out;


reg [3:0] count;



always @ (posedge CLK_in or negedge RSTn)
begin

if(!RSTn)

begin

count <= 4'b0;

end

else if(count == 4'd9)

begin

count <= 4'b0;

end

else

begin

count <= count + 4'd1;

end

end


always @ (posedge CLK_in or negedge RSTn)
begin

if(!RSTn)

begin

CLK_out <= 1'b0;

end

else if(count == 4'd9)

begin

CLK_out <= ~CLK_out;

end
end


endmodule

qiudanyi1

回复 1# qiudanyi1

因为板子上的晶振是20M，是cylconeII的芯片，PLL无法得到1M的时钟，所以，自己写了一个20分频的代码，发现分频后的时钟不是很稳定，求助，谢谢