[全职] Synopsys武汉 IP Center 热招ASIC/ Analog Engineer for DDR USB

Domiliu

二线城市 待遇丰厚 ！！

If you have any interest in the position, please send your bilingual resume as

attachments to
dmliu@synopsys.com

Subject of your email should be “Your Name_ University_ Applied Position Title_ Location”

1\ Job Title: Digital IP Designer ( ASIC Design or Verification_
USB DDR MIPI SATA)

Location: Wuhan

http://search.51job.com/job/53774338,c.html

Job responsibilities include understanding connectivity protocols like SATA, MIPI, SDMMC, AMBA, HDMI and working on the design/directed verification of designs in such protocols.

Be able to implement test benches and test cases in HDL like Verilog is needed.

Requirements:

- Has BSEE in EE with 3+ years of relevant experience or MS with 1+ years of relevant experience in one or more of the following areas:

- Has good background in RTL design and directed verification. Hands on experience with Verilog coding and Simulation tools

-Prior ASIC/IP directed verification skills with essential knowledge of Verilog/ System Verilog

-Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background

2\Job Title: Mix-signal IP Designer (Digital Design or Verification for

SerDes/ DDR PHY)

Location: Wuhan

Job Responsibilities:

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Develop and execute verification for IP level functional features related to DDR memory system.

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Work closely with Design/Macro teams to identify the milestones and quality metrics of the project that includes scoping, tracking and delivery.

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Participate in test environment infra and regression infra development, testbench development in VMM/SystemVerilog/C++, test cases development and debug.

Requirements

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Must have BSEE in EE with 6+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:

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Verification experience of IP core or ASIC Design for DDR memory system or mix-signal system.

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Hands on experience with creating test plan and test environment from Functional Specifications/ Test Environment Specifications with verification methodology of VMM/UVM.

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Hands on experience with System Verilog/ VERA coding and Simulation tools; Knowledge of C++/ OOPs Concepts.

3\ Job Title: Synopsys Analog Design/Layout Engineer

Location: Wuhan

http://search.51job.com/job/55817591,c.html

Job Responsibilities:

Design Engineer will be a part of a team developing high speed analog integrated circuits and responsible for designing innovative analog, RF and mixed-signal integrated circuits; developing circuit specifications working from published protocols and standards; and, selecting/creating circuit architectures based on practical experience and knowledge of current circuit literature.

Analog Layout is responsible for layout design of innovative analog, RF and mixed-signal integrated circuits;

Requirements:

-BSc in Electrical or Computer Engineering with 5+ years of experience, or MSc with 3+ years of experience, or PhD with 1+ years of experience.

-The successful candidate must possess a solid understanding of specialization area plus working knowledge of one other related area;

- Has the ability to resolve issues in creative ways; exercise judgment in selecting methods and techniques to obtain solutions; execute projects from start to completion; contribute to moderately complex aspects of a project; and, determines and develops recommendations to solutions.

- Layout Engineer must be experienced with physical layout and verification tools such as Virtuso , Laker, Calibre, Hercules and have layout design experience for advanced process node like 40nm, 28nm.