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clc1~clc5外部脉冲输入，cs和LED为数码管显示输出，
-- Quartus II VHDL Template
-- 计数统计
library ieee;
use ieee.std_logic_1164.all;
entity exp6 is
port
(
clc1,clc2,clc3,clc4,clc5 : in std_logic;
cs,LED  ut std_logic_vector(7 downto 0)
);
end exp6;
-- 统计模块
architecture tongji of exp6 is
begin
cs<="11111110";
process(clc1,clc2,clc3,clc4,clc5)
variable c1,c2,c3,c4,c5,sum:integer:=0;
begin
if clc1'event and clc1='1' then c1:=c1+1;
end if;
if clc2'event and clc2='1' then c2:=c2+1;
end if;
if clc3'event and clc3='1' then c3:=c3+1;
end if;
if clc4'event and clc4='1' then c4:=c4+1;
end if;
if clc5'event and clc5='1' then c5:=c5+1;
end if;
sum:=c1+c2+c3+c4+c5;
if sum>=15 then
c1:=0;
c2:=0;
c3:=0;
c4:=0;
c5:=0;
end if;
case sum is
when 0 => LED<="11000000";
when 1 => LED<="11111001";
when 2 => LED<="10100100";
when 3 => LED<="10110000";
when 4 => LED<="10011001";
when 5 => LED<="10010010";
when 6 => LED<="10000010";
when 7 => LED<="11111000";
when 8 => LED<="10000000";
when 9 => LED<="10010000";
when 10 => LED<="10001000";
when 11 => LED<="10000011";
when 12 => LED<="11000110";
when 13 => LED<="10100001";
when 14 => LED<="10000110";
when 15 => LED<="10001110";
when others => LED<="11000000";
end case;
end process;
end tongji;
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发表于 2014-6-27 19:49:12
