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发表于 2014-7-17 20:18:46
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Hi, i think u have no exp about development pdk.
And u can get the pdk source code(GTE source code) from cadence offical web.
In that, you can get lots of detail information how to design a pcell in GTE and generate it by PAS.
For your last question
pcell means parameterized cell, which not only integrates the IC design experience, but also passed Foundry verification with DRC/LVS. So u can directly use them in your design.
Besides, pcell also contains: CDF(Component Description Format), which can transfer parameter into pcell to generate the layout.
qcell means quick cell (in my mind) which just support very simple functions, such as change width/length for a mos and etc. In my opinion, qcell is a simple "pcell". |
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