请教一个关于彩灯程序的问题

clarence1990

最近在做一个设计，题目是这样的：设计一个多路彩灯控制器，能够在四种不同的彩灯花样之间进行循环变化，并可设置花型变化的节奏，且可进行复位。然后我设计完程序之后，编译通过，下载在Cyclone的EP1C12Q240C8上能百分百下载成功，但是没有实验现象，即板上的灯都是暗的，请教各位大神这是什么原因，源程序如下：
时序控制电路的Vhdl源程序

--SXKZ.VHD

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SXKZ IS

PORT(CHOSE_KEY:IN STD_LOGIC;

CLK_IN:IN STD_LOGIC;

CLR:IN STD_LOGIC;

CLK:OUT STD_LOGIC);

END ENTITY SXKZ;

ARCHITECTURE ART OF SXKZ IS

SIGNAL CLLK:STD_LOGIC;

BEGIN

PROCESS(CLK_IN,CLR,CHOSE_KEY)IS

VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN

IF CLR='1' THEN
——当CLR等于‘1’时清零，否则正常工作

CLLK<='0';TEMP:="000";

ELSIF RISING_EDGE(CLK_IN)THEN

IF CHOSE_KEY='1' THEN

IF TEMP="011" THEN

TEMP:="000";

CLLK<=NOT CLLK;

ELSE

TEMP:=TEMP+'1';

END IF;

——当CHOSE_KEY=‘1’时产生基准时钟频率的1/4的时钟信号

——否则产生基准时钟频率的1/8的时钟信号

ELSE

IF TEMP="111"THEN

TEMP:="000";

CLLK<=NOT CLLK;

ELSE

TEMP:=TEMP+'1';

END IF;

END IF;

END IF;

END PROCESS;

END ARCHITECTURE ART;

显示控制电路的VHDL源程序

--XSKZ.VHD

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY XSKZ IS

PORT(CLK:IN STD_LOGIC;

CLR:IN STD_LOGIC;

LED:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END ENTITY XSKZ;

ARCHITECTURE ART OF XSKZ IS

TYPE STATE IS(S0,S1,S2,S3,S4);

SIGNAL CURRENT_STATE:STATE;

SIGNAL FLOWER:STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

PROCESS(CLR,CLK)IS

CONSTANT F1:STD_LOGIC_VECTOR(7 DOWNTO 0):="01010101";

CONSTANT F2:STD_LOGIC_VECTOR(7 DOWNTO 0):="10101010";

CONSTANT F3:STD_LOGIC_VECTOR(7 DOWNTO 0):="10011001";

CONSTANT F4:STD_LOGIC_VECTOR(7 DOWNTO 0):="01100110";

——四种花型定义

BEGIN

IF CLR='1'THEN

CURRENT_STATE<=S0;

ELSIF RISING_EDGE(CLK)THEN

CASE CURRENT_STATE IS

WHEN S0=>

FLOWER<="ZZZZZZZZ";

CURRENT_STATE<=S1;

WHEN S1=>

FLOWER<=F1;

CURRENT_STATE<=S2;

WHEN S2=>

FLOWER<=F2;

CURRENT_STATE<=S3;

WHEN S3=>

FLOWER<=F3;

CURRENT_STATE<=S1;

WHEN OTHERS=>

FLOWER<=F1;

CURRENT_STATE<=S1;

END CASE;

END IF;

END PROCESS;

LED<=FLOWER;

END ARCHITECTURE ART;

顶层文件

--CDKZQ.VHD

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CDKZQ IS

PORT(CLK_IN:IN STD_LOGIC;

CLR:IN STD_LOGIC;

CHOSE_KEY:IN STD_LOGIC;

LED:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END ENTITY CDKZQ;

ARCHITECTURE ART OF CDKZQ IS

COMPONENT SXKZ IS

PORT(CHOSE_KEY:IN STD_LOGIC;

CLK_IN:IN STD_LOGIC;

CLR:IN STD_LOGIC;

CLK:OUT STD_LOGIC);

END COMPONENT SXKZ;

COMPONENT XSKZ IS

PORT(CLK:IN STD_LOGIC;

CLR:IN STD_LOGIC;

LED:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END COMPONENT XSKZ;

SIGNAL S1:STD_LOGIC;

BEGIN

U1:SXKZ PORT MAP(CHOSE_KEY,CLK_IN,CLR,S1);

U2:XSKZ PORT MAP(S1,CLR,LED);

END ARCHITECTURE ART;

不知道我的程序有没有写错，请大神不吝指正，万分感谢！