我在CDL IN页面填写了Reference Lib为analogLib,Device-Map file是自己写的,只有nfet和pfet。
==>1. no connect line ?
2. Reference Lib needs to have your process ex: XXX_018um
Hi mpig,
1. What is connect line in map file? Can you provide an example?
2. May be the process is incomplete, it's not provided by foundry and from elsewhere. I just use it for study purpose.
1. What is connect line in map file? Can you provide an example?
==>not in map file
can you provide the schematic when your cdlin, and check the mos has connection line or not?
2. May be the process is incomplete, it's not provided by foundry and from elsewhere. I just use it for study purpose.
==>does the schematic has mos and the mos characteristic (w/l, type) is the same with your cdl?
It does have connect line and mos, the size is correct too.
But some input has become output and output has become input, in schematic view.
For example A is input in symbol but became output in sch,
Y is output in symbol but became input in sch.
It does have connect line and mos, the size is correct too.
But some input has become output and output has become input, in schematic view.
For example A is input in symbol but became output in sch,
Y is output in symbol but became input in sch.
==>Sorry, I don't know how to solve this problem.
I solve it manually.
Hope someone know how to solve it.