sigma delta ADC 的死区（dead zone）问题

朱立平

回复 40# win9401


   This question dependents on how many bits you need to setting.
    first open loop BW * close loop time constant = 1
    => 1 time constant = 1.5 bit (since log2(exp) ~ 1.5)
    => OP operation time = slewing rate time + linear setting time


    1. We can approximate the maximum slewing rate time = VDD*C/I
    2. If we want to settling to 24 bits (ideal case)
       then 24 bits / 1.5bit = 16 => We need 16 close loop time constants
       But consider the process variation I suggest that you can take 1 time constant for settling 1 bit.
       Then the answer will be 24 close loop time constants to settling 24 bits for linear setting time.



       =>That means to settling N bits we need N close loop time constants+VDD*C/I.



       Give you a thumb of rule: Open loop OP BW = 8~10 Fs

ralphtw

who is right ?!

lostmj

学习学习~~~可是还没有结果。。。

lishiliang

说好的“包你设计SDM ADC行云流水”呢？？？
怪蜀黍就是喜欢骗人。。。。

alfredchn

回复 42# ralphtw


   Give you a thumb of rule: Open loop OP BW = 8~10 Fs

这个和前面的推论是否有点不符合？


24bit ADC = 24 time constants = 24/open loop OP BW


If open loop OP BW = 10Fs, then


24/10Fs=2.4Ts, OP的稳定时间大于时钟周期？？？

mixasic

回复 10# 朱立平


   这个与的dead zone有关吗？？？？

mixasic

回复 1# xiwanghebe


   There is a book named "Understanding Delta-Sigma Data Converters"

mixasic

There is a book named "Understanding Delta-Sigma Data Converters"

go on

mixasic

回复 15# jiang330226

顶10000下

mixasic

回复 23# 朱立平

期待您的大作，此帖我收藏！