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Qualifications
MS in EE/CS/ME.
Minimum of five years experience.
Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
Candidate should be familiar with as System verilog, VMM/OVM/UVM verification methdology.
Candidate should be familiar with industry standard ASIC design and verification tools and flow.
Good knowledge ddr protocol and computer system achitecture would be an added advantage.
Good knowledge of Perl and shell programming would be an added advantage.
Responsibilities:
-Understanding the expected functionality of designs.
-Developing testing and regression plans.
-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.
Requirements:
Experience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.
KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.
If you interested in the job, pls sent your cv to: hr@kthr.com, thanks!
“KT人才”微信也可查询职位啦!打开手机微信,搜号码“KTHR_COM”或查找微信公众帐号“KT人才”即可添加,欢迎大家关注!(关注成功后输入”KT“即可查询职位!) |
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