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楼主 |
发表于 2014-5-5 20:05:55
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源程序
module shift_reg(clk,clken,data_in,data_out);
input clk;
input clken;
input [7:0] data_in;
output [7:0] data_out;
/*always @(posedge clk)
begin
data_cnt=data_cnt+8'd1;
end*/
shift1 u1(
.clock(clk),
.clken(clken),
.shiftin(data_cnt),
.shiftout(data_out));
endmodule
测试程序:
initial
begin
clk=0;
data_in=8'b0;
clken=1'b0;
end
always #10 clk=~clk;
initial
begin
#100 clken=1'b1;
#200 clken=1'b0;
#100 clken=1'b1;
#200 clken=1'b0;
#100 clken=1'b1;
#200 clken=1'b0;
#100 clken=1'b1;
#200 clken=1'b0;
#100 clken=1'b1;
#200 clken=1'b0;
#100 clken=1'b1;
end
always @(posedge clk)
begin
if(clken)
data_in=data_in+1'b1;
end
endmodule
modelsim-ase编译正确,仿真时出错 |
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