xilinx的pll问题，看看这个问题怎么解决

574920045

ERRORlace:1113 - Unroutable Placement! A BUFIO / PLL clock component pair have been found that are not placed at a
   routable BUFIO / PLL site pair. The BUFIO component <SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_1> is placed at site
   <BUFIO2_X3Y7>. The corresponding PLL component <u_pll1/pll_base_inst/PLL_ADV> is placed at site <LL_ADV_X0Y1>. The
   BUFIO can use the fast path between the BUFIO and the PLL if the BUFIO is in TOPor BOTTOM edge and both the BUFIO &
   PLL are placed in the same half of the device (TOP or BOTTOM). This placement is UNROUTABLE in PAR and therefore,
   this error condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf
   file to demote this message to a WARNING in order to generate an NCD file. This NCD file can then be used in FPGA
   Editor to debug the problem. A list of all the COMP.PINS used in this clock placement rule is listed below. These
   examples can be used directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN "u_pll1/pll_base_inst/PLL_ADV.CLKIN1" CLOCK_DEDICATED_ROUTE = FALSE; >
ERRORack:1654 - The timing-driven placement phase encountered an error.

jxbuaaee

log不是写了吗，直接ucf里添加括号里的约束
These
   examples can be used directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN "u_pll1/pll_base_inst/PLL_ADV.CLKIN1" CLOCK_DEDICATED_ROUTE = FALSE; >

ccofcy

可以按log里面这个建议把error变成warning，让程序跑下去，然后用FPGA Editor来找问题，不过应该还是得想办法解决的，试试换一下输入管脚？或者如果对PLL做了区域约束把约束去掉试试？

haitaox

CLK的输入位置吧，和PLL距离太远了。
你指定了PLL的位置了？

574920045

回复 4# haitaox


    这个制定pll的位置不会用啊！怎么指定啊！

haitaox

你用了多少个pll

jxbuaaee

这个应该是pll的一个输出直接输出到pad上，所以会出这样的错误。

emicleung

不知道什么问题，鼎一个先。。。