Cadence北京招Processor Verification Engineer

kengteng

关键词：CS/软件工程专业；硕士；计算机体系结构

工作地点：北京东城区北三环东路北京环球贸易中心

联系邮箱：cecilyl@cadence.com

1. ProcessorVerification Engineer

Cadence-Tensilicais a leading provider of configurable embedded processor technology and DSPsfor various markets.

JobDescription:

1. As amember of the DSP engineering group you will be responsible for verification ofadvanced DSP cores and their instruction set architectures and hardwareimplementations.

2. Youwill implement architectural simulation testbenches in C/C++/RTL, writeC/assembly language diagnostics, assertion checkers or coverage monitors tomeet target verification goals.

3. Youwill also assist with developing testplans, debugging failures and analyzingcoverage information.

4. Youwill work closely with the market-specific DSP teams, Design Verification, andRTL and EDA teams.

RequiredSkills:

1. Knowledge of DSPs, instructions sets, computerarithmetic concepts. processor architecture concepts

2. Good knowledge of C/C++

3. Working knowledge of Verilog and popular EDAsimulators and testbench methodologies

4. Knowledge of scripting languages such asMakefile/Perl is desired

5. Knowledge of assembly programming and programmingin a high level language such as C will be a plus

6. Good English communication skills – both writtenand verbal

7. MSor PhD degree in EE/CS/Communication, etc.