状态机时序问题

风展位

利用状态机设计时序电路用于检测二进制序列10010，Verilog 代码如下：module seqdet(x,clk,rst,z,state);
input clk,x,rst;
output z,state;
reg [2:0] state;

parameter IDLE='d0,A='d1,B='d2,

C='d3,D='d4,E='d5;
always @(posedge clk)

if(!rst)

state<=IDLE;

else



case(state)

IDLE
: if(x)

state<=A;

else

state<=IDLE;

A
:
if(!x)

state<=B;

else

state<=A;

B
:
if(!x)

state<=C;

else

state<=B;

C
:if(x)

state<=D;

else

state<=IDLE;

D
:if(!x)

state<=E;

else

state<=A;

E
:if(x)

state<=A;

else

state<=C;

default
:
state<=IDLE;
endcase

assign z=(state==D&&x==0)?1:0;
endmodule


其testbech测试模块源代码如下：

`timescale 1ns/1ns
module seqdet_tb();
reg clk,rst;
reg [23:0] data;
wire z,x;
wire [2:0] state;
assign x=data[23];
always #10 clk=~clk;
always @(posedge clk)

data={data[22:0],data[23]};
initial

begin


clk=0;

rst=1;

#2 rst=0;

#30 rst=1;

data='b1100_1011_0000_1001_0100;

#500 $stop;

end
seqdet m(.x(x),.clk(clk),.rst(rst),.z(z),.state(state));
endmodule


输出z能够满足，但是state的时序变化总是落后于数据x一个周期，求助解释！

立青

检测序列可以不用状态机写吧?

sina4321

感觉不用状态机更简单，x直接进移位寄存器比较就可以了