吉他哥,那个MIG生成的ddr控制器我当做子模块,加上一个循环读写测试模块,然后封装在top顶层模块内就会报错::ConstraintSystem:58 - Constraint <NET
"memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;> [mig_37.ucf(36)]: NET
"memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode
" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST
"memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*"
TIG;> [mig_37.ucf(38)]: INST
"memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_s
oft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*"
does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <NET
"memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG;>
[mig_37.ucf(43)]: NET
"memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_s
oft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" does not match
any design objects.
ERROR:ConstraintSystem:59 - Constraint <NET
"memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";>
[mig_37.ucf(57)]: NET "memc3_infrastructure_inst/sys_clk_ibufg" not found.
Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:NgdBuild:924 - input pad net 'c3_sys_clk' is driving non-buffer
primitives:
如果用MIG生成的控制器当做顶层模块,循环读写测试模块在控制器内部实现,那么就可以,这是为什么啊?难道mig生成的控制器只能当顶层模块,不能当子模块吗?
##################################################################################
# Timing Ignore constraints for paths crossing the clock domain
##################################################################################
NET "memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "c?_pll_lock" TIG;
NET "memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ##This path exists for DDR2 only
############################################################################
## Memory Controller 3
## Memory Device: DDR2_SDRAM->MT47H64M16XX-25
## Frequency: 312.5 MHz
## Time Period: 3200 ps
## Supported Part Numbers: MT47H64M16HR-25
############################################################################
############################################################################
## Clock constraints
############################################################################
NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 3.2 ns HIGH 50 %;
############################################################################
您说的是删掉这部分的约束吗?