tsmc 130nm pdk (cdb)

RF007_2008 · 发表于 2014-11-28 18:17:18

可供学习的好东西

法兰西之梦 · 发表于 2014-11-29 21:34:03

好东东，谢谢

sea11038 · 发表于 2014-11-29 22:56:17

谢谢分享！

奥古拉斯 · 发表于 2014-11-30 11:47:07

感谢分享，学习

dafaa · 发表于 2014-12-3 04:06:01

有没有45nm的？想学习一下高速电路。

tuguoping1989 · 发表于 2014-12-10 15:30:42

就两个包？

iceplanet · 发表于 2015-1-3 11:35:43

谢谢楼主分享

iceplanet · 发表于 2015-1-3 11:59:23

though it spend me a lot of money, thanks for sharing

iceplanet · 发表于 2015-1-3 12:03:33

Though it spend me a lot of money, thanks for sharing

Ryan67 · 发表于 2015-1-9 01:00:51

Hi,
I'm new in Cadence and I'm designing circuits with TSMC0.13um PDK. My circuit contains 8 layers, but I don't know; how to place a via between two layers? for example metal via between met1 and met2.
I'm trying to do this in schematic, may be this is not possible in the schematic? because in the vias folder of my KitDesign TSMC90nm there are only symbolic and layout folders? if this is correct in which step, we can add vias between layers and via_gnd to take their influence in the performance of the designed circuits (during simulation with cadence).
I will appreciate your help

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