FPGA VGA

曦玄

module
VGA
(
//
VGA Side

oVGA_R,

oVGA_G,

oVGA_B,

oVGA_HS,

oVGA_VS,

oVGA_SYNC,

oVGA_BLANK,

oVGA_CLOCK,

//
Control Signal

iCLK,

iRST_N
);

//
VGA Side
output
reg
[9:0]
oVGA_R;
output
reg
[9:0]
oVGA_G;
output
reg
[9:0]
oVGA_B;
output
reg
oVGA_HS;
output
reg
oVGA_VS;
output
oVGA_SYNC;
output
oVGA_BLANK;
output
oVGA_CLOCK;
//
Control Signal
input
iCLK;
input
iRST_N;

//
Internal Registers
reg
[10:0]
H_Cont;
reg
[10:0]
V_Cont;
////////////////////////////////////////////////////////////
//
Horizontal
Parameter
parameter
H_FRONT
=
16;
parameter
H_SYNC
=
96;
parameter
H_BACK
=
48;
parameter
H_ACT
=
640;
parameter
H_BLANK
=
H_FRONT+H_SYNC+H_BACK;
parameter
H_TOTAL
=
H_FRONT+H_SYNC+H_BACK+H_ACT;
parameter   H_BAN=400;
////////////////////////////////////////////////////////////
//
Vertical Parameter
parameter
V_FRONT
=
11;
parameter
V_SYNC
=
2;
parameter
V_BACK
=
31;
parameter
V_ACT
=
480;//480
parameter
V_BLANK
=
V_FRONT+V_SYNC+V_BACK;
parameter
V_TOTAL
=
V_FRONT+V_SYNC+V_BACK+V_ACT;
////////////////////////////////////////////////////////////
assign
oVGA_SYNC
=
1'b1;
//
This pin is unused.
assign
oVGA_BLANK
= ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK));

assign
oVGA_CLOCK
=
~CLOCK;
always @(posedge iCLK or negedge iRST_N)
begin
  if(!iRST_N)
        begin
        oVGA_R <= 10'd0;
        oVGA_G <= 10'd0;
        oVGA_B <= 10'd0;
        end
   else  begin
    //RGB信号在显示期间正常输出，行、场消隐期间被清零
     oVGA_R <= (H_Cont >= H_BLANK && H_Cont <= H_TOTAL &&
                V_Cont >= V_BLANK && V_Cont <= V_TOTAL )
                ? 10'd0 : 10'd0;
     oVGA_G <= (H_Cont >= H_BLANK && H_Cont <= H_TOTAL &&
                V_Cont >= V_BLANK && V_Cont <= V_TOTAL )  
                ? 10'd0 : 10'd0;
     oVGA_B <= (H_Cont >= H_BLANK && H_Cont <= H_TOTAL &&

             V_Cont >= V_BLANK && V_Cont <= V_TOTAL )  
                ? 10'd1 : 10'd0;
      end
end/*
assign
oVGA_R
=
10'd1000000000;
assign
oVGA_G
=
10'd1000000000;
assign
oVGA_B
=
10'd1000000000;*/

//
Horizontal Generator: Refer to the pixel clock
reg CLOCK;

always@(posedge iCLK)
CLOCK<=~CLOCK;



always@(posedge CLOCK or negedge iRST_N)
begin

if(!iRST_N)

begin

H_Cont
<=
0;

oVGA_HS
<=
1;

end

else

begin

if(H_Cont<H_TOTAL)

H_Cont
<=
H_Cont+1'b1;

else

H_Cont
<=
0;

//
Horizontal Sync

if(H_Cont<=H_FRONT-1)
//
Front porch end

oVGA_HS
<=
1'b0;

if(H_Cont<=H_FRONT+H_SYNC-1)
//
Sync pulse end

oVGA_HS
<=
1'b1;



end
end

//
Vertical Generator: Refer to the horizontal sync
always@(posedge oVGA_HS or negedge iRST_N)
begin

if(!iRST_N)

begin

V_Cont
<=
0;

oVGA_VS
<=
1;

end

else

begin

if(V_Cont<V_TOTAL)

V_Cont
<=
V_Cont+1'b1;

else

V_Cont
<=
0;

//
Vertical Sync

if(V_Cont<=V_FRONT-1)
//
Front porch end

oVGA_VS
<=
1'b0;

if(V_Cont<=V_FRONT+V_SYNC-1)
//
Sync pulse end

oVGA_VS
<=
1'b1;



end
end
endmodule

曦玄

我这样直接让显示屏显示一种颜色原理行吗？