multiple driver(s)错误ISE

rui211

1. `timescale 1ns / 1ps
   
2. 
   
3. module my_top
   
4.   (
   
5.     //clk,  
   
6.     video,
   
7.     horiz_sync_out,
   
8.     vert_sync_out,
   
9.     video_de,
   
10. 
    
11.     RESET,
    
12.     IIC_MAIN_SDA,
    
13.     IIC_MAIN_SCL,
    
14.     CLK_P,
    
15.     CLK_N,
    
16.     clock_generator_0_CLKOUT2_pin
    
17.   );
    
18.   
    
19. // input clk;
    
20.   output[15:0] video;
    
21.   output horiz_sync_out,vert_sync_out;
    
22.   output video_de;
    
23.   
    
24.   input RESET;
    
25.   inout IIC_MAIN_SDA;
    
26.   inout IIC_MAIN_SCL;
    
27.   input CLK_P;
    
28.   input CLK_N;
    
29. 
    
30. wire clk;
    
31. wire clock_generator_0_CLKOUT1_pin;
    
32. // wire clock_generator_0_CLKOUT3_pin;
    
33. 
    
34. 
    
35. output clock_generator_0_CLKOUT2_pin;
    
36. 
    
37. //clock_generator_0_CLKOUT1_pin <= clock_generator_0_CLKOUT3_pin;
    
38. 
    
39.   mys_top
    
40.     mysystem (
    
41.       .RESET ( RESET ),
    
42.       .IIC_MAIN_SDA ( IIC_MAIN_SDA ),
    
43.       .IIC_MAIN_SCL ( IIC_MAIN_SCL ),
    
44.       .CLK_P ( CLK_P ),
    
45.       .CLK_N ( CLK_N ),
    
46.       .clock_generator_0_CLKOUT1_pin (clock_generator_0_CLKOUT1_pin ),
    
47.       .clock_generator_0_CLKOUT2_pin(clock_generator_0_CLKOUT2_pin)
    
48.     );
    
49.   (* BOX_TYPE = "user_black_box" *)
    
50.   user_logic
    
51.    user(  .clk(clk),
    
52.           .video(video),
    
53.           .horiz_sync_out(horiz_sync_out),
    
54.           .vert_sync_out(vert_sync_out),
    
55.           .video_de(video_de)
    
56.                                                 );
    
57. //assign clk=clock_generator_0_CLKOUT1_pin;
    
58. IBUFG clk_bufg_i
    
59.   (
    
60.     .O (clk),
    
61.     .I (clock_generator_0_CLKOUT1_pin)
    
62.   );
    
63. 
    
64. 
    
65. endmodule
    
66. 
    

复制代码

ERROR:NgdBuild:455 - logical net 'clock_generator_0_CLKOUT1_pin' has multiple
   driver(s):
ERROR:NgdBuild:770 - IBUFG 'clk_bufg_i' and IBUFG 'IBUFG' on net 'clk' are lined
   up in series. Buffers of the same direction cannot be placed in series.
ISE仿真报错，

                               
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这个方法也改过了，还是报错，用的是ISE14.4求指点

buley

clock_generator_0_CLKOUT1_pin 在 mysystem 改成其他的试试呢

wrl201

clock_generator_0_CLKOUT1_pin 这个信号是怎么来的，看看mysystem 这个模块