Computer Architecture Complexity And Correctness Risc Design

leasor · 发表于 2014-3-24 07:28:55

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Computer Architecture Complexity And Correctness Risc Design
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N THIS BOOK we develop at the gate level the complete design of a
pipelined RISC processor with delayed branch, forwarding, hardware
interlock, precise maskable nested interrupts, caches, and a fully IEEE-
compliant floating point unit. The design is completely modular. This
permits us to give rigorous correctness proofs for almost every part of the
design. Also, because we can compute gate counts and gate delays, we can
formally analyze the cost effectiveness of all parts of the design.

Computer Architecture Complexity And Correctness Risc Design.pdf (2.6 MB, 下载次数: 351 )

qmdong · 发表于 2014-3-25 23:48:36

新书吗？楼主？

pupukid · 发表于 2014-3-26 01:34:22

old book !

zlhrsy · 发表于 2014-3-26 09:02:44

看看先

apteye · 发表于 2014-4-1 11:50:16

correctness proofs

lujunfeng111 · 发表于 2014-4-13 18:55:24

2000年出版的书了。

ID2007 · 发表于 2014-4-27 10:34:15

还行，参考下

fufuck · 发表于 2014-4-27 12:20:51

Good, thanks for sharing

厉害198989 · 发表于 2014-4-28 23:15:57

看看吧！

machinecat-007 · 发表于 2014-5-1 13:32:51

看介绍的话，是一本不错的书

Computer Architecture Complexity And Correctness Risc Design

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