Layout Consideration to Prevent electrical overstress failure (High-Voltage)

semico_ljj · 发表于 2014-3-18 22:00:14

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Layout Consideration and Circuit Solution to Prevent
EOS Failure Induced by LatchupTest in a High-Voltage Integrated Circuits

Abstract—This paper presented a practical industry case of
electrical overstress (EOS) failure induced by the latchup test
in high-voltage integrated circuits (ICs). By using proper layout
modification and additional circuit, the unexpected EOS failure,
which is caused by negative-current-triggered latchup test, can
be successfully solved. The new design with proposed solutions
has been verified in the 0.6-μm 40-V Bipolar CMOS DMOS
(BCD) process to pass the test for at least 500-mA trigger current,
which shows high negative-current-latch-up immunity without
overstressdamage,comparedwiththeprotectionofonlytheguard
ring.Suchsolutionscanbeadoptedtoimplementhigh-voltage-ap-
plicableICproducttomeettheindustryrequirementforthemass
productionof ICmanufactures and applications.
IndexTerms—Electricaloverstress(EOS),high-voltageCMOS,
latchup,regulator.

tshiu · 发表于 2014-3-24 09:29:38

Where's the attached?

xiaowanzi88 · 发表于 2014-3-24 10:18:03

Layout Consideration to Prevent electrical overstress failure.pdf (1.04 MB , 下载次数: 291 )

fenglinping · 发表于 2014-4-25 10:08:49

student321 · 发表于 2014-4-25 19:44:04

read_ljr · 发表于 2014-7-23 14:24:07

谢谢楼主

beyond某人 · 发表于 2014-9-14 15:25:33

回复 3# xiaowanzi88

版主好人

hujiaomianhao · 发表于 2014-9-14 18:59:03

hao dong xi!!!

chenxz_123456 · 发表于 2014-9-16 12:35:37

谢谢分享

piao · 发表于 2015-3-14 00:15:27

a good one. Thanks for sharing

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[资料] Layout Consideration to Prevent electrical overstress failure (High-Voltage)

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