global net connection时在typical.lib文件中没发现电源pin和地pin

xialishui1987 · 发表于 2014-3-5 10:17:12

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各位大侠，在encounter中进行global net connection时，
我想在typical.lib文件中寻找std_cell的电源pin和地pin，
可是发现里面并没有，不知道问题出在哪里，以下是typical.lib的内容
library(typical) {
  /* general attributes */
  delay_model : table_lookup;
  in_place_swap_mode : match_footprint;
  library_features(report_delay_calculation);
  /* documentation attributes */
  revision : 1.1;
  date : "Mon Aug 18 19:02:58 PDT 2003";
  comment : "Copyright (c) 2003 Artisan Components, Inc.  All Rights Reserved.";
  /* unit attributes */
  time_unit : "1ns";
  voltage_unit : "1V";
  current_unit : "1mA";
  pulling_resistance_unit : "1kohm";
  leakage_power_unit : "1pW";
  capacitive_load_unit (1.0,pf);
  /* operation conditions */
  nom_process    : 1;
  nom_temperature : 25;
  nom_voltage    : 1.8;
  operating_conditions(typical) {
process : 1;
temperature : 25;
voltage : 1.8;
tree_type : balanced_tree
  }
  default_operating_conditions : typical;
  /* threshold definitions */
  slew_lower_threshold_pct_fall : 30.0;
  slew_upper_threshold_pct_fall : 70.0;
  slew_lower_threshold_pct_rise : 30.0;
  slew_upper_threshold_pct_rise : 70.0;
  input_threshold_pct_fall    : 50.0;
  input_threshold_pct_rise    : 50.0;
  output_threshold_pct_fall    : 50.0;
  output_threshold_pct_rise    : 50.0;
  slew_derate_from_library    : 0.5;
  /* default attributes */
  default_leakage_power_density : 0.0;
  default_cell_leakage_power : 0.0;
  default_fanout_load : 1.0;
  default_output_pin_cap : 0.0;
  default_inout_pin_cap : 0.0035;
  default_input_pin_cap : 0.0035;
  default_max_transition : 3.0;
  /* templates */
  lu_table_template(delay_template_7x1) {
variable_1 : input_net_transition;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
  }
  power_lut_template(energy_template_7x1) {
variable_1 : input_transition_time;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
  }
  lu_table_template(delay_template_7x7) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
index_2 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
  }
  power_lut_template(energy_template_7x7) {
variable_1 : input_transition_time;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
index_2 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
  }
  power_lut_template(energy_template_1x7) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
  }
  power_lut_template(energy_template_7x3x3) {
variable_1 : input_transition_time;
variable_2 : total_output_net_capacitance;
variable_3 : equal_or_opposite_output_net_capacitance;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
index_2 ("1000, 1001, 1002");
index_3 ("1000, 1001, 1002");
  }
  power_lut_template(passive_energy_template_1x7) {
variable_1 : input_transition_time;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
  }
  lu_table_template(setup_template_3x3) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000, 1001, 1002");
index_2 ("1000, 1001, 1002");
  }
  lu_table_template(hold_template_3x3) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000, 1001, 1002");
index_2 ("1000, 1001, 1002");
  }
  lu_table_template(recovery_template_3x3) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000, 1001, 1002");
index_2 ("1000, 1001, 1002");
  }
  lu_table_template(removal_template_3x3) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000, 1001, 1002");
index_2 ("1000, 1001, 1002");
  }
  /* k-factors */
  k_process_cell_leakage_power : 0;
  k_temp_cell_leakage_power : 0;
  k_volt_cell_leakage_power : 0;
  k_process_internal_power : 0;
  k_temp_internal_power : 0;
  k_volt_internal_power : 0;
  k_process_rise_transition : 1;
  k_temp_rise_transition : 0;
  k_volt_rise_transition : 0;
  k_process_fall_transition : 1;
  k_temp_fall_transition : 0;
  k_volt_fall_transition : 0;
  k_process_setup_rise : 1;
  k_temp_setup_rise : 0;
  k_volt_setup_rise : 0;
  k_process_setup_fall : 1;
  k_temp_setup_fall : 0;
  k_volt_setup_fall : 0;
  k_process_hold_rise : 1;
  k_temp_hold_rise : 0;
  k_volt_hold_rise : 0;
  k_process_hold_fall : 1;
  k_temp_hold_fall : 0;
  k_volt_hold_fall : 0;
  k_process_min_pulse_width_high : 1;
  k_temp_min_pulse_width_high : 0;
  k_volt_min_pulse_width_high : 0;
  k_process_min_pulse_width_low : 1;
  k_temp_min_pulse_width_low : 0;
  k_volt_min_pulse_width_low : 0;
  k_process_recovery_rise : 1;
  k_temp_recovery_rise : 0;
  k_volt_recovery_rise : 0;
  k_process_recovery_fall : 1;
  k_temp_recovery_fall : 0;
  k_volt_recovery_fall : 0;
  k_process_cell_rise : 1;
  k_temp_cell_rise : 0;
  k_volt_cell_rise : 0;
  k_process_cell_fall : 1;
  k_temp_cell_fall : 0;
  k_volt_cell_fall : 0;
  k_process_wire_cap : 0;
  k_temp_wire_cap : 0;
  k_volt_wire_cap : 0;
  k_process_wire_res : 0;
  k_temp_wire_res : 0;
  k_volt_wire_res : 0;
  k_process_pin_cap : 0;
  k_temp_pin_cap : 0;
  k_volt_pin_cap : 0;
  /* pad attributes */
  output_voltage(GENERAL) {
vol : 0.4;
voh : VDD - 0.4;
vomin : -0.5;
vomax : VDD + 0.5;
  }
  input_voltage(CMOS) {
vil : 0.3 * VDD;
vih : 0.7 * VDD;
vimin : -0.5;
vimax : VDD + 0.5;
  }
  input_voltage(TTL) {
vil : 0.8;
vih : 2;
vimin : -0.5;
vimax : VDD + 0.5;
  }
  /* wire-loads */
  wire_load("smic18_wl10") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 66.667;
fanout_length (1,66.667);
  }
  wire_load("smic18_wl20") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 133.334;
fanout_length (1,133.334);
  }
  wire_load("smic18_wl30") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 200.001;
fanout_length (1,200.001);
  }
  wire_load("smic18_wl40") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 266.668;
fanout_length (1,266.668);
  }
  wire_load("smic18_wl50") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 333.335;
fanout_length (1,333.335);
  }
  /* QA wire-load */
  wire_load("ForQA") {
resistance : 0;
capacitance : 1;
area : 1;
slope : 1;
fanout_length(1,0);
fanout_length(10,0);
  }
  /* additional header data */

/* end of header section */
/* append the cell blocks to this file and close */
/* with a final } */

xialishui1987 · 发表于 2014-3-5 10:23:58

哪位帮忙回答一下？谢谢

xialishui1987 · 发表于 2014-3-5 10:45:51

I have found the power and gnd pin names of std cells in the lef file

nbuzs · 发表于 2014-3-5 10:50:38

lib库中可以用add_pg_pin_to_lib添加电源地引脚

xialishui1987 · 发表于 2014-3-5 18:28:11

回复 4# nbuzs

好的，谢谢

[求助] global net connection时在typical.lib文件中没发现电源pin和地pin

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