第一次用k7，前面都通过了，就在生成bit文件时报错，

aspire_su

WARNINGIT:701 - PAD symbol "clk_fpga" has an undefined IOSTANDARD.
WARNINGlace:1399 - A clock IOB / BUFGCTRL clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
   IOB component <clk_fpga> is placed at site <AF23>. The corresponding BUFGCTRL
   component <clk_fpga_BUFGP/BUFG> is placed at site <BUFGCTRL_X0Y0>. The clock
   IO can use the fast path between the IOB and the Clock Buffer if the IOB is
   placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL
   sites in its half of the device (TOP or BOTTOM). You may want to analyze why
   this problem exists and correct it. This is normally an ERROR but the
   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <clk_fpga.PAD>
   allowing your design to continue. This constraint disables all clock placer
   rules related to the specified COMP.PIN. The use of this override is highly
   discouraged as it may lead to very poor timing results. It is recommended
   that this error condition be corrected in the design.

neufeifatonju

你做的什么工程，我估计是约束的问题

acgoal

根本原因是clk_fpga没有用专用时钟管脚，你可以ignore掉这个warning，应该不会报错。或者把clk_fpga绑定到那个bank的专用时钟管脚上去。