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[讨论] 利用块RAM实现数据延迟的一些问题

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发表于 2013-12-15 22:22:05 | 显示全部楼层 |阅读模式

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这个是利用块RAM实现a、b两路数据延迟，数据位宽都为32，其中a路延迟16个数据周期，b路延迟8个数据周期，代码如下：


   

        

                

  2. `timescale 1ns / 1ps
  3. //////////////////////////////////////////////////////////////////////////////////
  4. // Company:
  5. // Engineer:
  6. //
  7. // Create Date:    20:51:45 12/15/2013
  8. // Design Name:
  9. // Module Name:    bram_delay
  10. // Project Name:
  11. // Target Devices:
  12. // Tool versions:
  13. // Description:
  14. //
  15. // Dependencies:
  16. //
  17. // Revision:
  18. // Revision 0.01 - File Created
  19. // Additional Comments:
  20. //
  21. //////////////////////////////////////////////////////////////////////////////////
  22. module bram_delay(
  23.     input wire clk,
  24.          input wire rst_n,
  25.          input wire[31:0] a_in,
  26.          input wire[31:0] b_in,
  27.          output reg[31:0] a_delay,
  28.          output reg[31:0] b_delay);
  29. /*************************************************************************/   
  30.          parameter DEL = 1;
  31. /*************************************************************************/
  32.     wire[5:0] a_addr;
  33.     wire[5:0] b_addr;
  34.          wire[31:0] douta;
  35.          wire[31:0] doutb;
  36.          reg[5:0] a_addr1 = 6'd0;
  37.          reg[5:0] a_addr2 = 6'd0;
  38.          reg[5:0] b_addr1 = 6'd32;
  39.          reg[5:0] b_addr2 = 6'd32;
  40.          reg wea = 1'b0;
  41.          reg web = 1'b0;
  42.          reg flag = 1'b0;
  43.          
  44. /**************************************************************************/
  45.     always @ ( posedge clk)
  46.              begin
  47.                       if( rst_n == 1'b0 )
  48.                                     begin
  49.                                              a_delay <= 32'b0;
  50.                                                   b_delay <= 32'b0;
  51.                                          end
  52.                                 else begin
  53.                       flag <= #DEL !flag;
  54.                                 if( flag == 1'b1)
  55.                                     begin
  56.                                              a_delay <= #DEL a_delay;
  57.                                                   b_delay <= #DEL b_delay;
  58.                                                   wea <= #DEL 1'b1;
  59.                                                   web <= #DEL 1'b1;
  60.                                                   a_addr2 <= #DEL a_addr2;
  61.                                                   b_addr2 <= #DEL b_addr2;
  62.                                                   if( a_addr1 == 6'd31)
  63.                                                       a_addr1 <= #DEL 6'd0;
  64.                                                   else
  65.                                                       a_addr1 <= #DEL a_addr1 + 6'b1;
  66.                                                   if( b_addr1 == 6'd63)
  67.                                                       b_addr1 <= #DEL 6'd0;
  68.                                                   else
  69.                                                       b_addr1 <= #DEL b_addr1 + 6'b1;
  70.                 end
  71.             else
  72.                           begin
  73.                               a_delay <= #DEL douta;
  74.                                         b_delay <= #DEL doutb;
  75.                                         wea <= #DEL 1'b0;
  76.                                         web <= #DEL 1'b0;
  77.                                         a_addr1 <= #DEL a_addr1;
  78.                                         b_addr1 <= #DEL b_addr1;
  79.                                         if( a_addr1 <= 6'd15)
  80.                                             a_addr2 <= #DEL a_addr1 + 6'd16;
  81.                                         else
  82.                                             a_addr2 <= #DEL a_addr1 - 6'd16;
  83.                                         if( b_addr1 <= 6'd39)
  84.                                             b_addr2 <= #DEL b_addr1 + 6'd24;
  85.                                         else
  86.                                             b_addr2 <= #DEL b_addr1 - 6'd8;
  87.                 end
  88.                                 end
  89.         end
  90. /*************************************************************************/

  92.     assign a_addr = !flag ? a_addr1 : a_addr2;
  93.          assign b_addr = !flag ? b_addr1 : b_addr2;
  94. /**************************************************************************/
  95.   bram_16 dut (
  96.   .clka(clk), // input clka
  97.   .wea(wea), // input [0 : 0] wea
  98.   .addra(a_addr), // input [5 : 0] addra
  99.   .dina(a_in), // input [15 : 0] dina
  100.   .douta(douta), // output [15 : 0] douta
  101.   .clkb(clk), // input clkb
  102.   .web(web), // input [0 : 0] web
  103.   .addrb(b_addr), // input [5 : 0] addrb
  104.   .dinb(b_in), // input [15 : 0] dinb
  105.   .doutb(doutb) // output [15 : 0] doutb
  106.    );                     

  108. endmodule

  109.         

   

    复制代码



这个程序功能能够实现，仿真结果也正确，但是却出现瑕疵，综合出现结果如下：


   

        

                

  2. WARNING:Xst:916 - "bram_delay.v" line 52: Delay is ignored for synthesis.
  3. WARNING:Xst:916 - "bram_delay.v" line 55: Delay is ignored for synthesis.
  4. WARNING:Xst:916 - "bram_delay.v" line 56: Delay is ignored for synthesis.
  5. WARNING:Xst:916 - "bram_delay.v" line 57: Delay is ignored for synthesis.
  6. WARNING:Xst:916 - "bram_delay.v" line 58: Delay is ignored for synthesis.
  7. WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
  8. WARNING:Xst:2211 - "ipcore_dir/bram_16.v" line 94: Instantiating black box module <bram_16>.
  9. WARNING:Xst:647 - Input <b_in<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  10. WARNING:Xst:647 - Input <a_in<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  11. WARNING:Xst:1710 - FF/Latch <b_delay_31> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  12. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_30> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  13. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_29> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  14. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_28> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  15. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_27> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  16. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_26> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  17. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_25> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  18. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_24> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  19. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_23> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  20. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_22> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  21. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_21> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  22. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_20> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  23. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_19> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  24. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_18> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  25. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_17> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  26. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <b_delay_16> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  27. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_31> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  28. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_30> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  29. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_29> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  30. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_28> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  31. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_27> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  32. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_26> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  33. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_25> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  34. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_24> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  35. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_23> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  36. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_22> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  37. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_21> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  38. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_20> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  39. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_19> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  40. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_18> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  41. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_17> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  42. WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <a_delay_16> (without init value) has a constant value of 0 in block <bram_delay>. This FF/Latch will be trimmed during the optimization process.
  43. WARNING:Xst:2404 -  FFs/Latches <b_delay<31:16>> (without init value) have a constant value of 0 in block <bram_delay>.
  44. WARNING:Xst:2404 -  FFs/Latches <a_delay<31:16>> (without init value) have a constant value of 0 in block <bram_delay>.

  45.         

   

    复制代码




对于a_delay和b_delay都已经初始化了的，为什么还出现这个问题？仿真图如下：
搜狗截图13年12月15日2214_1.jpg




望各位坛友支支招，在此谢谢了！！
create, Design

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发表于 2013-12-16 09:57:21 | 显示全部楼层
如果只是延时32的话，完全可以用移位寄存器(分布式RAM)实现，用BRAM浪费了
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 楼主| 发表于 2013-12-16 11:46:58 | 显示全部楼层
回复 2# huxiaokai2005
如果考虑到优化的话，确实用分布式RAM比较好，但问题是为什么会出现上述问题？
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发表于 2013-12-16 11:51:14 | 显示全部楼层
看这样子是没有复位，楼主把rst_n低电平的时间弄长一点。
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 楼主| 发表于 2013-12-16 13:01:15 | 显示全部楼层
回复 4# 110500623

刚开始在复位时，我是写有延时的，结果还是一样，所以后来我就直接删除了！
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发表于 2013-12-16 18:58:28 | 显示全部楼层
数据要先赋值，然后读取啊，你开始仿真，还没有把RAM整个初始化完，那写一段地址的数据进去，读另一段地址的数据出来，那段还没初始化过，自然会是z了。

flag怎么激励的？
按你的写法，flag应是渐段式激励吧？写1后再写0，然后等延迟若干后地址的数据输出。
另外，对a, b路的关系觉得很诡异，按你的想法，a, b路是关系平等的两路数据，只是分别延迟不同地址而已吧？那你用个真双口是为了什么？真双口的数据对A口和B口来说，内容是共享的，那岂不是a, b路数据相互冲突了？
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 楼主| 发表于 2013-12-16 22:46:15 | 显示全部楼层
回复 6# eaglelsb
你说的应该没错，应该就是初始化时间不够造成的。。。我知道真双口RAM的内容是共享的，所以我固定前段地址（0—31）只能写a数据，后段（32—63）数据只能写b数据，而且输出地址也是有设置了的，故我觉得虽然共享，但它们的数据是不会矛盾的，不会有冲突！不知这样是否妥当？？
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发表于 2013-12-17 14:31:37 | 显示全部楼层
回复 7# gateway91


有这样处理自然没问题，不会冲突就好，你还可以直接用两个单口RAM啊，二者在RAM的使用面积上是一致的
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 楼主| 发表于 2013-12-17 15:37:53 | 显示全部楼层
回复 8# eaglelsb
是啊，考虑到数据方面，最后还是改成分布式的了，利用器件原语，节省资源。。。总之，谢谢了！
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发表于 2015-7-24 10:03:16 | 显示全部楼层
受教了，谢谢
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